參數(shù)資料
型號(hào)： TSC251G2DXXX-24IA
英文描述： IC CYCLONE III FPGA 80K 484 FBGA
中文描述： 微控制器
文件頁(yè)數(shù)： 47/63頁(yè)
文件大?。?/td> 878K
代理商： TSC251G2DXXX-24IA
Rev. A - May 7, 1999
47
TSC80251G2D
11.4 AC Characteristics - Serial Port in Shift Register Mode
Definition of symbols
Table 51. Serial Port Timing Symbol Definitions
Timings
Table 52. Serial Port AC Timing -Shift Register Mode; V
DD
= 2.7 to 5.5 V, T
A
= -40 to 85
°
C
Note:
1. For high speed versions only.
Waveforms
Note:
1. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.
Figure 25. Serial Port Waveforms - Shift Register Mode
Signals
Conditions
D
Data In
H
High
Q
Data Out
L
Low
X
Clock
V
Valid
X
No Longer Valid
Symbol
Parameter
12 MHz
16 MHz
24 MHz
(1)
Unit
Min
Max
Min
Max
Min
Max
T
XLXL
T
QVXH
T
XHQX
T
XHDX
T
XHDV
Serial Port Clock Cycle Time
998
749
500
ns
Output Data Setup to Clock Rising Edge
833
625
417
ns
Output Data hold after Clock Rising Edge
165
124
82
ns
Input Data Hold after Clock Rising Edge
0
0
0
ns
Clock Rising Edge to Input Data Valid
974
732
482
ns
T
XLXL
T
XHDV
T
XHDX
T
QVXH
T
XHQX
Set TI
(1)
Set RI
(1)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
RXD (In)
RXD (Out)
TXD
0
1
2
3
4
5
6
7
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