參數(shù)資料
型號(hào)： TSC251G2DXXX-24CB
英文描述： IC CYCLONE III FPGA 80K 484 FBGA
中文描述： 微控制器
文件頁數(shù)： 7/63頁
文件大?。?/td> 878K
代理商： TSC251G2DXXX-24CB
Rev. A - May 7, 1999
7
TSC80251G2D
P1.0:7
I/O
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups. P1 provides interrupt capability
for a keyboard interface.
P2.0:7
I/O
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
A15:8
P3.0:7
I/O
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
PROG#
I
Programming Pulse input
The programming pulse is applied to this input for programming the on-chip EPROM/
OTPROM.
PSEN#
O
Program Store Enable/Read signal output
PSEN# is asserted for a memory address range that depends on bits RD0 and RD1 in
UCONFIG0 byte (see Table 13, Page 15).
Read or 17
th
Address Bit (A16)
Read signal output to external data memory depending on the values of bits RD0 and RD1
in UCONFIG0 byte (see Table 13, Page 15).
RD#
O
P3.7
RST
I
Reset input to the chip
Holding this pin high for 64 oscillator periods while the oscillator is running resets the device.
The Port pins are driven to their reset conditions when a voltage greater than V
IH1
is applied,
whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be reset by connecting
a capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal
operation.
RXD
I/O
Receive Serial Data
RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1,
2 and 3.
I
2
C Serial Clock
When I
2
C controller is in master mode, SCL outputs the serial clock to slave peripherals.
When I
2
C controller is in slave mode, SCL receives clock from the master controller.
P3.0
SCL
I/O
P1.6
SCK
I/O
SPI Serial Clock
When SPI is in master mode, SCK outputs clock to the slave peripheral. When SPI is in
slave mode, SCK receives clock from the master controller.
I
2
C Serial Data
SDA is the bidirectional I
2
C data line.
P1.6
SDA
I/O
P1.7
SS#
I
SPI Slave Select Input
When in Slave mode, SS# enables the slave mode.
P1.4
T1:0
I/O
Timer 1:0 External Clock Inputs
When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count.
T2
I/O
Timer 2 Clock Input/Output
For the timer 2 capture mode, T2 is the external clock input. For the Timer 2 clock-out mode,
T2 is the clock output.
P1.0
T2EX
I
Timer 2 External Input
In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-
reload mode, a falling edge causes the timer 2 register to be reloaded. In the up-down counter
mode, this signal determines the count direction: 1= up, 0= down.
P1.1
TXD
O
Transmit Serial Data
TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1,
2 and 3.
P3.1
VDD
PWR
Digital Supply Voltage
Connect this pin to +5V or +3V supply voltage.
VPP
I
Programming Supply Voltage
The programming supply voltage is applied to this input for programming the on-chip EPROM/
OTPROM.
Signal
Name
Type
Description
Alternate
Function
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