參數(shù)資料
型號: TSC251G1DXXX-L16CB
英文描述: IC CYCLONE III FPGA 5K 256-UBGA
中文描述: 微控制器
文件頁數(shù): 43/63頁
文件大?。?/td> 878K
代理商: TSC251G1DXXX-L16CB
Rev. A - May 7, 1999
43
TSC80251G2D
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 18. External Bus Cycle: Data Write (Non-Page Mode)
Waveforms in Page Mode
Notes:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
2. A page hit (i.e., a code fetch to the same 256-byte “page” as the previous code fetch) requires one state (2·T
OSC
);
a page miss requires two states (4·T
OSC
).
3. During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
Figure 19. External Bus Cycle: Code Fetch (Page Mode)
T
WHLH
T
AVWL2(1)
T
AVWL1(1)
T
LHAX(1)
T
LLAX
T
WHQX
T
WHAX
P2/A16/A17
P0
WR#
ALE
T
LHLL(1)
T
WLWH(1)
Data Out
A15:8/A16/A17
T
AVLL(1)
T
QVWH
A7:0
D7:0
T
LLAX
T
AVDV2(1)
T
AVDV1(1)
T
LHAX(1)
T
AVRL(1)
T
RHDZ1
T
RHDX
T
RLAZ
T
AXDX
T
AVDV3(1)
P0/A16/A17
P2
PSEN#
(3)
ALE
T
LHLL(1)
A7:0/A16/A17
T
AVLL(1)
T
LLRL(1)
T
RLDV(1)
Page Miss
(2)
Page Hit
(2)
T
RHAX
A7:0/A16/A17
D7:0
D7:0
A15:8
Instruction In
Instruction In
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