參數(shù)資料
型號: TSC251G1DXXX-L16CB
英文描述: IC CYCLONE III FPGA 5K 256-UBGA
中文描述: 微控制器
文件頁數(shù): 39/63頁
文件大小: 878K
代理商: TSC251G1DXXX-L16CB
Rev. A - May 7, 1999
39
TSC80251G2D
11. AC Characteristics - Commercial & Industrial
11.1 AC Characteristics - External Bus Cycles
Definition of symbols
Table 44. External Bus Cycles Timing Symbol Definitions
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 45 and Table 46 list the AC timing parameters for the TSC80251G2D derivatives with no wait states. External
wait states can be added by extending PSEN#/RD#/WR# and or by extending ALE. In these tables, Note 2 marks
parameters affected by one ALE wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states.
Figure 16 to Figure 21 show the bus cycles with the timing parameters.
Signals
Conditions
A
Address
H
High
D
Data In
L
Low
L
ALE
V
Valid
Q
Data Out
X
No Longer Valid
R
RD#/PSEN#
Z
Floating
W
WR#
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