參數(shù)資料
型號(hào): TSC251G1DXXX-24IB
英文描述: IC CYCLONE III FPGA 5K 256 FBGA
中文描述: 微控制器
文件頁數(shù): 18/63頁
文件大?。?/td> 878K
代理商: TSC251G1DXXX-24IB
Rev. A - May 7, 1999
18
TSC80251G2D
7.2 Size and Execution Time for Instruction Families
Table 20. Summary of Add and Subtract Instructions
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Add
Subtract
Add with Carry
Subtract with Borrow
ADD <dest>, <src>
SUB <dest>, <src>
ADDC <dest>, <src>
SUBB <dest>, <src>
dest opnd
dest opnd + src opnd
dest opnd
dest opnd - src opnd
(A)
(A) + src opnd + (CY)
(A)
(A) - src opnd - (CY)
Mnemonic
<dest>, <src>
(1)
Comments
Binary Mode
Source Mode
Bytes
States
Bytes
States
ADD
A, Rn
Register to ACC
1
1
2
2
A, dir8
Direct address to ACC
2
1
(2)
2
1
(2)
A, @Ri
Indirect address to ACC
1
2
2
3
A, #data
Immediate data to ACC
2
1
2
1
ADD / SUB
Rmd, Rms
Byte register to/from byte register
3
2
2
1
WRjd, WRjs
Word register to/from word register
3
3
2
2
DRkd, DRks
Dword register to/from dword register
3
5
2
4
Rm, #data
Immediate 8-bit data to/from byte register
4
3
3
2
WRj, #data16
Immediate 16-bit data to/from word register
5
4
4
3
DRk, #0data16
16-bit unsigned immediate data to/from dword register
5
6
4
5
Rm, dir8
Direct address (on-chip RAM or SFR) to/from byte register
4
3
(2)
3
2
(2)
WRj, dir8
Direct address (on-chip RAM or SFR) to/from word register
4
4
3
3
Rm, dir16
Direct address (64K) to/from byte register
5
3
(3)
4
(4)
3
(3)
4
(3)
4
2
(3)
3
(4)
2
(3)
3
(3)
WRj, dir16
Direct address (64K) to/from word register
5
4
Rm, @WRj
Indirect address (64K) to/from byte register
4
3
Rm, @DRk
Indirect address (16M) to/from byte register
4
3
ADDC / SUBB
A, Rn
Register to/from ACC with carry
1
1
2
2
A, dir8
Direct address (on-chip RAM or SFR) to/from ACC with
carry
2
1
(2)
2
1
(2)
A, @Ri
Indirect address to/from ACC with carry
1
2
2
3
A, #data
Immediate data to/from ACC with carry
2
1
2
1
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