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參數(shù)資料
| 型號： | TRF2056PWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20 |
| 封裝： | PLASTIC, SOP-20 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 327K |
| 代理商： | TRF2056PWR |
TRF2056
LOW VOLTAGE 1.2GHz FRACTIONALN/INTEGERN SYNTHESIZER
SLWS111– NOVEMBER 2000
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
loop enable/disable
The main and auxiliary loops can be enabled and disabled by the contents of the enable bits EM and EA,
respectively. When disabled, all currents in the RF input stages are switched off; the bias currents for the
respective charge-pump circuits are switched off as well. When both loops are disabled (EM = EA = 0), the
reference input stage currents are switched off. The reference chain can be turned off because the serial
interface operates independent of the reference input for the loading of serial words.
Table 7. Loop Enable/Disable
EM
EA
ENABLED
DISABLED
0
Main, Auxiliary, Reference
0
1
Auxiliary, Reference
Main
1
0
Main, Reference
Auxiliary
1
Main, Auxiliary, Reference
speed-up mode
When the main synthesizer frequency is changed, it may be desirable to increase the loop bandwidth for a short
time in order to achieve a faster locking speed. The proportional charge-pump current is increased and the
integral charge-pump current is switched on for the duration of speed-up mode. The
charge-pump current plans
section illustrates how the charge-pump currents are a function of the external resistor RN and the
programmable coefficients CN, CL, and CK.
lock detect
The lock condition of the PLL is defined as a phase difference of less than a
±1 cycle on the reference input
REFIN. The LOCK terminal can be polled to determine the synthesizer lock condition of either or both loops.
The lock detect function is described by the Boolean expression:
LOCK
+ LD
Main )
EM
LD
Aux )
EA
test modes
The LOCK terminal may be used for test operations by terminating terminal 19 to ground. When test modes are
enabled, the LOCK terminal is connected to internal nodes of the TRF2056 device. Test modes are enabled
by writing ones to the two LSBs of the E-Word. Test modes are disabled by terminating terminal 19 to VCC
through a 10-k
pull-up resistor.
Table 8. Test Modes
T1
T0
MODE
0
Buffered output of the fractional accumulator
0
1
Buffered output of the auxiliary divider
1
0
Buffered output of the main divider
1
Buffered output of the reference divider
The test mode can verify the division ratio of the reference divider, the auxiliary divider, and the main divider
and prescaler.
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