參數(shù)資料
型號: TRF1121_07
廠商: Texas Instruments, Inc.
英文描述: Dual VCO/PLL Synthesizer With IF Up-Converter
中文描述: 雙的VCO / PLL頻率合成器與中頻直至轉(zhuǎn)換器
文件頁數(shù): 3/27頁
文件大?。?/td> 1356K
代理商: TRF1121_07
www.ti.com
TRF1121
TRF1221
SLWS170A–APRIL 2005–REVISED DECEMBER 2005
TERMINAL FUNCTIONS
TERMINAL
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
I/O
TYPE
DESCRIPTION
NAME
CP2O
LD2
LF2
DATA
VCCD2
FR
VCCD1
FRBP
EN
LF1
LD1
CP1O
LO1BPA
O
O
O
I
I
I
I
I
O
I
O
O
O
O
Analog
Digital
Analog
Digital
Digital
Power
Analog
Power
Analog
Digital
Analog
Digital
Analog
Analog
Synthesizer 2 charge pump output
Synthesizer 2 lock detect output, High is locked.
Lock detect filter capacitor for LO2, 0.01
μ
F typical 100 k
pull-up
(1)
Serial interface data input
Serial interface clock input
+5 V power for digital
18-MHz reference clock input, HCMOS input. (DC level = 2.5 V)
+5 V power for digital
Reference frequency bypass. Internally biased to 2.5 V.
Serial interface load enable (active high)
Lock detect filter capacitor for LO1, 0.01
μ
F typical 100 k
(1)
Synthesizer 1 lock detect output, High is locked.
Synthesizer 1 charge pump output
Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to
any other pin.
VCO synthesizer 1 tuning port
Bypass capacitor for LO1 0.1
μ
F (min) DCV =1.0 V
VCC for LO1
Ground
15
16
17
LO1TUN
LO1BPB
VCCLO1
I
Analog
Analog
Power
Power
O
I
18, 19, 20, 29, GND
30, 37, 39, 42
21
22
23
24
25
26
27
28
31
32
33
34
35
36
38
40
41
43
BBIN
BBIP
VCCUPC
GAIN[0]
GAIN[1]
GAIN[2]
GAIN[3]
GAIN[4]
IFON
VCCIF
IFOP
TXON
EXTLO2IN
EXTLO2IP
VCCLO2
LO2ON
LO2OP
LO2BBPA
I
I
I
I
I
I
I
I
Analog
Analog
Power
Digital
Digital
Digital
Digital
Digital
Analog
Power
Analog
Digital
Analog
Analog
Power
Analog
Analog
Analog
Baseband IF input (2 k
diff) negative, dc-coupled, Internal voltage is 4 V DC
Baseband IF input (2 k
diff) positive, dc-coupled, Internal voltage is 4 V DC
+5V power Analog
Gain control bit 0 (LSB) – Logic low induces 1-dB attenuation
Gain control bit 1 – Logic low induces 2-dB attenuation
Gain control bit 2 – Logic low induces 4-dB attenuation
Gain control bit 3 – Logic low induces 8-dB attenuation
Gain control bit 4 (MSB) – Logic low induces 16-dB attenuation
IF analog output (100
diff ) negative, dc-coupled, Internal voltage is 2.1 V DC
+5 V power Analog
IF analog output (100
diff ) positive, dc-coupled, Internal voltage is 2.1 V DC
IF amplifier enable active high
External input for LO2 (differential) negative and logic level for VCO select.
External input for LO2 (differential) positive and logic level for VCO select.
VCC for LO2 A and B
LO2 output (differential) Negative and positive VCC bias (+5 V) for LO buffer amp.
LO2 output (differential) Positive and positive VCC bias (+5 V) for LO buffer amp.
Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to
any other pin.
LO2B Tune Port
Bypass cap. for LO2B 0.1
μ
F (min) DCV = 1 V
Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to
any other pin.
LO2A tune port
Bypass capacitor for LO2A 0.1
μ
F (min ) DCV = 1 V
Back side of package has metal base that must be grounded for thermal and RF performance
O
I
O
I
I
I
I
O
O
O
44
45
46
LO2BTUN
LO2BBPB
LO2ABPA
I
Analog
Analog
Analog
O
O
47
48
Back
LO2ATUN
LO2ABPB
I
Analog
Analog
O
(1)
Current leakage on the order of 10
μ
A through the capacitor or by any other means from either LF pin can cause false loss of lock
signals. The two pullup resistors (R16 and R17) in
Figure 23
reduce this sensitivity.
3
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