參數(shù)資料
型號: TPS79628KTTRG3
廠商: Texas Instruments, Inc.
英文描述: ULTRALOW-NOISE, HIGH PSRR, FAST, RF, 1A LOW-DROPOUT LINEAR REGULATORS
中文描述: 超低噪聲,高PSRR,快速,射頻低壓差線性穩(wěn)壓器1A條
文件頁數(shù): 2/33頁
文件大?。?/td> 899K
代理商: TPS79628KTTRG3
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating temperature range (unless otherwise noted)
(1)
PACKAGE DISSIPATION RATINGS
TPS796xx
SLVS351I–SEPTEMBER 2002–REVISED MAY 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION
(1)
PRODUCT
TPS796
xx
yyy
z
V
OUT(2)
XX
is nominal output voltage (for example, 28 = 2.8V, 01 = Adjustable).
YYY
is package designator.
Z
is package quantity.
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at
www.ti.com
.
Output voltages from 1.3V to 4.9V in 100mV increments are available; minimum order quantities may apply. Contact factory for details
and availability.
(2)
UNIT
–0.3V to 6V
–0.3V to V
IN
+ 0.3V
6V
Internally limited
2kV
500V
See Dissipation Ratings Table
–40
°
C to +150
°
C
–65
°
C to +150
°
C
V
IN
range
V
EN
range
V
OUT
range
Peak output current
ESD rating, HBM
ESD rating, CDM
Continuous total power dissipation
Junction temperature range, T
J
Storage temperature range, T
stg
(1)
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE
DDPAK
SOT223
3
×
3 SON
BOARD
High-K
(1)
Low-K
(2)
High-K
(1)
R
θ
JC
2
°
C/W
15
°
C/W
1.2
°
C/W
R
θ
JA
23
°
C/W
53
°
C/W
40
°
C/W
(1)
The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch
×
3-inch (7,5-cm
×
7,5-cm), multilayer board with 1-ounce
internal power and ground planes and 2-ounce copper traces on top and bottom of the board.
The JEDEC low-K (1s) board design used to derive this data was a 3-inch
×
3-inch (7,5-cm
×
7,5-cm), two-layer board with 2-ounce
copper traces on top of the board.
(2)
2
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