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參數(shù)資料
| 型號： | TPS70802PWP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 線性穩(wěn)壓 |
| 英文描述： | DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS |
| 中文描述： | 兩用低壓差電壓帶的劈開SVS的系統(tǒng)集成穩(wěn)壓器的輸出電壓 |
| 文件頁數(shù)： | 27/29頁 |
| 文件大?。?/td> | 449K |
| 代理商： | TPS70802PWP |
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TPS70845, TPS70848, TPS70851, TPS70858, TPS70802
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
SLVS301B – JUNE 2000 – REVISED OCTOBER 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
The TPS708xx low dropout regulator family provides dual regulated output voltages with independent enable
functions. These devices provide fast transient response and high accuracy with small output capacitors, while
drawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good
(PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated features
provide a complete power solution.
The TPS708xx, unlike many other LDOs, features very low quiescent current which remains virtually constant
even with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is
directly proportional to the load current through the regulator (IB = IC/β). The TPS708xx uses a PMOS transistor
to pass current; because the gate of the PMOS is voltage driven, operating current is low and stable over the
full load range.
pin functions
enable (EN1 and EN2)
The EN terminals are inputs which enable or shut down each respective regulator. If EN is at a voltage high
signal the respective regulator is in shutdown mode. When EN goes to voltage low, then the respective regulator
is enabled.
power good (PG1 and PG2)
The PG terminals are open drain, active high outputs which indicate the status of each respective regulator.
When the VOUT1 reaches 95% of its regulated voltage, PG1 goes to a high impedance state. When the VOUT2
reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedance
state when its respective output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage.
The open drain outputs of the PG terminals require a pullup resistor.
manual reset pin (MR)
MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR
(RESET) occurs. The terminal has a 6-
A pullup current to VIN1.
sense (VSENSE1, VSENSE2)
The sense terminals of fixed-output options must be connected to the regulator outputs, and the connection
should be as short as possible. Internally, the sense terminal connects to high-impedance wide-bandwidth
amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is
essential to route the sense connection in such a way as to minimize/avoid noise pickup. Adding RC networks
between sense terminals and VOUTS to filter noise is not recommended because it can cause the regulators
to oscillate.
FB1 and FB2
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external
feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them
in such a way as to minimize/avoid noise pickup. Adding RC networks between FB terminals and VOUTS to filter
noise is not recommended because it can cause the regulators to oscillate.
RESET indicator
The TPS708xx features a RESET (SVS, POR, or power on reset). RESET can be used to drive power on reset
circuitry or a low-battery indicator. RESET is an active low, open drain output which indicates the status of the
manual reset pin (MR). When MR is in high impedance state, RESET goes to a high impedance state after a
120 ms delay. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output
pin can be connected to MR. The open drain output of the RESET terminal requires a pullup resistor. If RESET
is not used, it can be left floating.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TPS70802PWP | 制造商:Texas Instruments 功能描述:IC DUAL ADJ LDO 20-HTSSOP 制造商:Texas Instruments 功能描述:IC, DUAL ADJ LDO 20-HTSSOP |
| TPS70802PWPG4 | 功能描述:低壓差穩(wěn)壓器 - LDO Dual-Output LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TPS70802PWPR | 功能描述:低壓差穩(wěn)壓器 - LDO Dual-Output LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TPS70802PWPRG4 | 功能描述:低壓差穩(wěn)壓器 - LDO Dual-Output LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TPS70845 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS |
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