參數(shù)資料
型號: TPS65124RGT
廠商: Texas Instruments, Inc.
英文描述: SINGLE-INDUCTOR QUADRUPLE-OUTPUT TFT LCD POWER SUPPLY
中文描述: 單電感翻兩番,輸出TFT LCD電源
文件頁數(shù): 6/23頁
文件大?。?/td> 706K
代理商: TPS65124RGT
www.ti.com
PIN ASSIGNMENTS
1
2
3
4
12
11
10
9
5
6
7
8
13
15
16
EN
RUN
ENVGL
ENVGH
F
F
A
V
PGND
BOOT
VGH
FBH
G
V
S
S
1
2
3
4
12
11
10
9
5
6
7
8
13
14
15
16
EN
RUN
AGND
AGND
F
F
A
V
PGND
BOOT
VGH
FBH
G
V
S
1
2
3
4
12
11
10
9
5
6
7
8
13
14
15
16
Exposed
Thermal Die*
AGND
EN
RUN
LDOIN
LDOOUT
F
F
A
V
PGND
BOOT
VGH
FBH
G
V
S
S
S
Exposed
Thermal Die*
AGND
14
Exposed
Thermal Die*
AGND
TPS65120/1/2
(TOP VIEW)
TPS65123
(TOP VIEW)
TPS65124
(TOP VIEW)
TPS65120, TPS65121, TPS65123, TPS65124
SLVS531–JUNE 2004
TERMINAL FUNCTIONS
TERMINAL
NAME
VIN
I/O
DESCRIPTION
NO.
15
I
This is the input voltage pin of the device.
This pin can either be the gate driver output to an external small P-Channel MOSFET (see application
section), or an active high control input. Pulling GATE above the 1.4 V logic-high level and RUN to a logic-low
level disables the integrated active power-down sequencing.
RUN controls the external P-Channel MOSFET. This pin must be terminated and not be left floating. Forcing
this pin to a logic-high level turns on the external MOSFET switch.
This is the enable pin of the multiple-output dc-to-dc converter. This pin must be terminated and not be left
floating. A simultaneous logic-high level on EN and RUN enables the converter and a logic-low shuts down
the device.
Connect the inductor to this pin. This pin is connected to the source of the high-side MOSFET switch.
Connect the inductor to this pin. This pin is connected to the drain of the low-side MOSFET switch.
Power ground. Connect to AGND underneath the IC.
Positive output
Provides a bootstrapped supply for the rectifier MOSFET driver, enabling the gate of the MOSFET to be
driven above the output voltage.
Main output
Feedback pin for the positive output voltage divider. Regulates to 1.213 V nominal.
Feedback pin for the negative output voltage divider. Regulates to 0 V nominal. Connect feedback resistor
divider between VGL and main output.
Feedback pin for the main output voltage divider. Regulates to 1.213V nominal.
Analog ground. Connect to power ground (PGND) underneath IC. Pins 3 and 4 are only used for AGND in
TPS65123.
Auxiliary linear regulator input. If this pin is connected to GND, the voltage regulator is disabled
(TPS65120/1/2). The low-dropout series-pass regulator (LDO) is enabled according to the GATE signal
timing.
Auxiliary linear regulator output (TPS65120/1/2).
Enable pin for negative output (TPS65124). This pin should be terminated and not be left floating.
Enable pin for positive output (TPS65124). This pin should be terminated and not be left floating.
GATE
16
I/O
RUN
2
I
EN
1
I
SWN
SWP
PGND
VGH
14
13
12
10
I/O
I/O
O
O
BOOT
11
O
VMAIN
FBH
8
9
I
I
FBL
5
I
FBM
6
I
AGND
7, 3, 4
LDOIN
3
I
LDOOUT
ENVGL
ENVGH
4
3
4
O
I
I
6
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