參數(shù)資料
型號(hào): TPS61170DRV
廠商: Texas Instruments, Inc.
英文描述: 1.2A High Voltage Boost Converter in 2x2mm2 QFN Package
中文描述: 1.2A的高電壓升壓轉(zhuǎn)換器2x2mm2 QFN封裝
文件頁(yè)數(shù): 12/22頁(yè)
文件大?。?/td> 405K
代理商: TPS61170DRV
www.ti.com
Low Bit
(Logic 0)
High Bit
(Logic 1)
t
Low
t
High
t
LOW
t
High
Easy Scale Timing, without acknowledge RFA = 0
DA7
0
t
Start
Static High
Static High
DATA IN
t
Start
T
EOS
T
EOS
DA0
0
RFA
0
D0
1
Address Byte
DATA Byte
Easy Scale Timing, with acknowledge RFA = 1
Static High
t
ACKN
Acknowledge
true
, Data Line
pulled down by
device
DATA IN
DATA OUT
Acknowledge
false
, no pull
down
Controller needs to
Pullup Data Line via a
resistor to detect ACKN
ACKN
DA7
0
Static High
T
EOS
t
valACK
DA0
0
RFA
1
D0
1
t
Start
t
Start
Address Byte
DATA Byte
TPS61170
SLVS789–NOVEMBER 2007
Table 2. EasyScale Bit Description (continued)
BIT
TRANSMISSION
DIRECTION
BYTE
NAME
DESCRIPTION
NUMBER
Acknowledge condition active 0, this condition will only be applied in case RFA bit is
set. Open drain output, Line needs to be pulled high by the host with a pullup
resistor. This feature can only be used if the master has an open drain output stage.
In case of a push pull output stage Acknowledge condition may not be requested!
ACK
OUT
Figure 16. EasyScale — Bit Coding
All bits are transmitted MSB first and LSB last.
Figure 16
shows the protocol without acknowledge request (Bit
RFA = 0),
Figure 16
with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address byte and data
byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least t
start
(2
μ
s) before
the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition is
needed prior to the device address byte. The transmission of each byte is closed with an End of Stream
condition for at least t
EOS
(2
μ
s).
12
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Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s):
TPS61170
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