參數(shù)資料
型號(hào): TPS61050YZG
廠商: Texas Instruments, Inc.
英文描述: 1.2-A HIGH POWER WHITE LED DRIVER 2-MHz SYNCHRONOUS BOOST CONVERTER WITH I2C COMPATIBLE INTERFACE
中文描述: 1.2 A的高功率白光LED I2C兼容接口的驅(qū)動(dòng)2 - MHz的同步升壓轉(zhuǎn)換器
文件頁(yè)數(shù): 23/45頁(yè)
文件大?。?/td> 1033K
代理商: TPS61050YZG
www.ti.com
SERIAL INTERFACE DESCRIPTION
I
2
C is a 2-wire serial interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is
idle
, both SDA and SCL lines are pulled high. All the I
2
C compatible devices connect to the I
2
C bus
through open drain I/O pins, SDA and SCL. A
master
device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A
slave
device
receives and/or transmits data on the bus under control of the master device.
F/S-MODE PROTOCOL
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in
Figure 42
All I
2
C-compatible devices should
recognize a start condition.
START Condition
DATA
CLK
STOP Condition
S
P
Data Line
Stable;
Data Valid
DATA
CLK
Change
of Data
Allowed
TPS61050
TPS61052
SLUS525–MARCH 2007
The TPS6105x device works as a
slave
and supports the following data transfer
modes
, as defined in the
I
2
C-Bus Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
power supply solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. Register contents remain intact as long as the supply voltage remains
above approximately 2 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as
F/S-mode in this document. The TPS6105x device supports 7-bit addressing; 10-bit addressing and general call
address are not supported. The device 7-bit address is defined as 011 0011.
Figure 42. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see
Figure 43
). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see
Figure 44
) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with
a slave has been established.
Figure 43. Bit Transfer on the Serial Interface
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