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參數(shù)資料
| 型號(hào)： | TPS5300DAP |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 231K |
| 代理商： | TPS5300DAP |
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TPS5300
IMVP MOBILE POWER SUPPLY CONTROLLER
SLVS334 – DECEMBER 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
4
ANAGND
Analog ground
BG
17
O
Bottom gate drive. BG is an output drive to the low-side synchronous rectifier FET.
Bootstrap. Connect a 1-
μ
F low ESR ceramic capacitor to PH to generate a floating drive for the high-side
FET driver.
BOOT
21
I
DROOP
10
I
Active voltage droop position voltage. DROOP is a voltage input used to set the amount of output-voltage,
set-point droop as a function of load current. The amount of droop compensation is set with a resistor divider
between IOUT and ANAGND. A voltage divider from VO to VSENSE_CORE sets the no load offset.
CLK voltage regulator. DRV_CLK drives an external NPN bipolar power transistor for regulating CLK
voltage to VREF_CLK.
DRV_CLK
1
O
DRVGND
16
Drive ground. Ground for FET drivers. Connect to FET PWRGND
DRV_IO
32
O
Drives an external NPN bipolar power transistor for regulating IO voltage to VREF_IO.
DT_SET
3
I
DT_SET sets the transition time for speed step output voltage positioning. Attach a capacitor from DT_SET
to ground to program time.
ENABLE_EXT
29
O
Open drain output. ENABLE_EXT enables external converters when the internal enable signal is high
(good), and disables when there is a fault with any regulator (OVP, UVP, OCPrr), VR_ON UVLO is low, or the
VBIAS UVLO is low. Can be connected to the enable terminal of an external linear regulator or switching
controller. A pullup resistor is required to set the desired voltage rail.
IS–
13
I
Current sense negative Kelvin connection. Connect to the node between the current sense resistor and the
output capacitors. Keep the PCB trace short and route trace next to the IS+ trace to help reduce loop
inductance noise pickup and cancel common mode noise through mutual coupling.
IS+
14
I
Current sense positive Kelvin connection. Connect to the node between the output inductor and the current
sense resistor. Keep the PCB trace short and route trace next to the IS-trace to help reduce loop inductance
noise and cancel common mode noise through mutual coupling.
IOUT
11
O
Current sense differential amplifier output. The voltage on IOUT equals 25 x (VI(+) – VI(–)) = 25 x
(R(sense)x IL).
Over current protection. Current limit trip point is set with a resistor divider between IOUT and
ANAGND. The
typical OCP trip point should be set at 1.30
×
I(max). The OCP voltage also sets the PSM automatic trip points.
Phase voltage node. PH is used for bootstrap low reference. PH connects to the junction of the high-side and
low-side FET’s.
OCP
9
I
PH
19
I/O
PSM/LATCH
12
I
PSM. Power saving mode boosts efficiency at low load current by automatically decreasing the switching
frequency toward the natural converter operating frequency. A logic low (<1.8) disables PSM, maintaining
the higher switching frequency range set by CT.
LATCH. Allows disabling fault latch. Recommend enabling fault latch protection
Sets a ramp on the feedback signal to increase the switching frequency. Add a resistor from PH to RAMP and
connect RAMP to VSENSE_CORE for a dc-coupled ramp. Add a capacitor from RAMP to VSENSE_CORE
to set an ac-coupled ramp.
RAMP
28
I
SLOWST
6
I
Slow start (soft start). A capacitor from SLOWST to GND sets the slowstart time for the ripple regulator and
the two linear regulators. The three converters will ramp up together while tracking the output voltage. A
current equal to IVrefb/5 charges the capacitor.
TG
20
O
Top gate drive. TG is an output drive to the high-side power switching FET’s. It is also used in the
anticross-conduction circuit to eliminate shoot-through current.
VBIAS
30
I
Analog VBIAS. It is recommended that at least a 1-
μ
F capacitor be connected to ANAGND. Supply from VCB
through RC filter
VCC
18
Supply voltage. VCC is the supply voltage for the FET drivers. Add an external resistor/capacitor filter from
VCC to VBIAS. It is recommended that a 1-
μ
F capacitor be connected to the DRVGND terminal.
VGATE
15
O
Logical and output of the combined core, IO, and CLK powergoods. VGATE outputs a logic high when all
(core, IO, CLK) output voltages are within 7% of the reference voltage. An open drain output allows setting to
desired voltage level through a pullup resistor.
P
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