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| 型號： | TPS5211PWP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH FREQUENCY PROGRAMMABLE HYSTERETIC REGULATOR CONTROLLER |
| 中文描述： | 可編程滯高頻穩(wěn)壓控制器 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大小： | 469K |
| 代理商： | TPS5211PWP |
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TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the
high-side FETs are on. The sampling network consists of an internal 60-
switch and an external ceramic hold
capacitor. Recommended value of the hold capacitor is between 0.033
μ
F and 0.1
μ
F. Internal logic controls
the turnon and turnoff of the sample/hold switch such that the switch does not turn on until the Vphase voltage
transitions high, and the switch turns off when the input to the high-side driver goes low. The sampling will occur
only when the high-side FETs are conducting current. The voltage on the IOUT pin equals 2 times the sensed
high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the
current sensing circuit.
droop compensation
The droop compensation network reduces the load transient overshoot/undershoot on V
O
, relative to V
REF
. V
O
is programmed to a voltage greater than V
REF
by an external resistor divider from V
O
to VSENSE to reduce the
undershoot on V
O
during a low-to-high load transient. The overshoot during a high-to-low load transient is
reduced by subtracting the voltage on DROOP from V
REF
. The voltage on IOUT is divided with an external
resistor divider, and connected to DROOP.
inhibit
INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers
are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart
capacitor is released and normal converter operation begins. When the system-logic supply is connected to
INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply
exceeds the input threshold voltage of the inhibit circuit. The 12-V supply and the system logic supply (either
5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The start threshold
is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator.
V
CC
undervoltage lockout (UVLO)
The undervoltage lockout circuit disables the controller while the V
CC
supply is below the 10-V start threshold
during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is
discharged. When V
CC
exceeds the start threshold, the short across the slowstart capacitor is released and
normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise
immunity.
slowstart
The slowstart circuit controls the rate at which V
O
powers up. A capacitor is connected between SLOWST and
ANAGND and is charged by an internal current source. The current source is proportional to the reference
voltage, so that the charging rate of C
SLOWST
is proportional to the reference voltage. By making the charging
current proportional to V
REF
, the power-up time for V
O
will be independent of V
REF
. Thus, C
SLOWST
can remain
the same value for all VID settings. The slowstart charging current is determined by the following equation:
I
slowstart
= I(VREFB) / 5 (amps)
Where I(VREFB) is the current flowing out of VREFB.
It is recommended that no additional loads be connected to VREFB, other than the resistor divider for setting
the hysteresis voltage. The maximum current that can be sourced by the VREFB circuit is 500
μ
A
.
The equation
for setting the slowstart time is:
t
SLOWST
= 5
×
C
SLOWST
×
R
VREFB
(seconds)
Where R
VREFB
is the total external resistance from V
REFB
to ANAGND.
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