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| 型號(hào)： | TPS51220ARTVR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, 333 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 24/53頁 |
| 文件大小： | 1380K |
| 代理商： | TPS51220ARTVR |
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RF[kW] +
1
105
sw [kHz]
IN(TYP)
OUT
OUT(MAX)
SW
IN(TYP)
(V
- V
) × V
1
L =
×
0.33 x I
x
V
f
R
SENSE +
V
OCL
I
OCL(PEAK)
Rgv + 0.1
I
OUT(MAX)
I
OCL(PEAK)
V
OUT
1
Gmv
Vdroop
Rgv[kW] + 200
I
OUT(MAX)
I
OCL(PEAK)
V
OUT[V]
Vdroop[mV]
0 +
5
p
I
OCL(PEAK)
1
V
OUT
Gmv
Rgv
Co
t
sw
3
Co u
15
p
I
OCL(PEAK)
1
V
OUT
Gmv
Rgv
sw
0 +
1
2p
ESR
Co
t
sw
3
Co u
3
2p
ESR
sw
SLUS897D – DECEMBER 2008 – REVISED FEBRUARY 2010
www.ti.com
(8)
3. Choose the inductor. The inductance value should be determined to give the ripple current of
approximately 25% to 50% of maximum output current. Recommended ripple current rate is about 30% to
40% at the typical input voltage condition, next equation uses 33%.
(9)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation.
4. Determine the OCL trip voltage threshold, V(OCL), and select the sensing resistor.
The OCL trip voltage threshold is determined by TRIP pin setting. To use a larger value improves the S/N
ratio. Determine the sensing resistor using next equation. IOCL(PEAK) should be approximately 1.5 × IOUT(MAX)
to 1.7 × IOUT(MAX).
(10)
5. Determine Rgv. Rgv should be determined from preferable droop compensation value and is given by next
equation based on the typical number of Gmv = 500mS.
(11)
(12)
If no-droop is preferred, attach a series RC network circuit instead of single resistor. Series resistance is
determined using Equation 12 . Series capacitance can be arbitrarily chosen to meet the RC time constant,
but should be kept under 1/10 of fo. For D-CAP mode, Rgv is used for adjusting ramp compensation. 10k is
a good value to start design with. 6k
to 20k can be chosen.
6. Determine output capacitance Co to achieve a stable operation using the next equation. The 0 dB frequency,
fo, should be kept under 1/3 of the switching frequency.
(13)
(14)
For D-CAP mode, fo is determined by the output capacitor’s characteristics as below.
(15)
(16)
For better jitter performance, a sufficient amount of feedback signal is required at VFBx pin. The
recommended signal level is approximately 30mV per tsw (switching period) of the ramping up rate, and more
than 4 mV of peak-to-peak voltage.
30
Copyright 2008–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS51220A
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