參數(shù)資料
型號(hào): TPS51220ARTVR
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: DUAL SWITCHING CONTROLLER, 333 kHz SWITCHING FREQ-MAX, PQCC32
封裝: 5 X 5 MM, PLASTIC, QFN-32
文件頁(yè)數(shù): 16/53頁(yè)
文件大?。?/td> 1380K
代理商: TPS51220ARTVR
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www.ti.com
SLUS897D – DECEMBER 2008 – REVISED FEBRUARY 2010
PWM FREQUENCY CONTROL
The TPS51220A has a fixed frequency control scheme with 180° phase shift. The switching frequency can be
determined by an external resistor which is connected between RF pin and GND, and can be calculated using
(1)
TPS51220A can also synchronize to more than 2.5 V amplitude external clock by applying the signal to the RF
pin. The set timing of channel 1 initiates at the raising edge (1.3 V typ) of the clock and channel 2 initiates at the
falling edge (1.1 V typ). Therefore, the 50% duty signal makes both channels 180° phase shift.
When the external clock synchronization is selected, the following conditions are required.
Remove RF resistor
Add clock signal before EN1 or EN2 turning on
The TPS51220A does NOT support switching frequency change on-the-fly. (neither from the switching frequency
set by the RF resistor to the external clock, nor vice versa)
Figure 41. Switching Frequency vs RF
180 Degrees Phase Shift and Blanking Time
The two channels of the SMPS operate 180 degrees phase shift. This scheme helps in reducing the input RMS
current. As a result, the device provides the benefits of saving the number and power loss of the input bulk
capacitors. To minimize interaction between the two channels caused by switching noise, blanking time is
implemented. The loop comparator output is masked during the blanking time to avoid false turning off the
channel.
There are two cases where the inter-channel communication can take place:
1. One channel's switching node falling edge is close to another channel's switching node rising edge.
2. One channel's switching node falling edge is close to another channel's switching node falling edge.
In both cases, the TPS51220A shows jitter inherent to the blanking time. Since the device is a fixed frequency
controller, the rising edge of the switching node is settled at the clock cycle. Consequently, jitter is observed at a
period of switching node falling edge. This jitter does not represent small signal instability. In fact, jittering is a
Copyright 2008–2010, Texas Instruments Incorporated
23
Product Folder Link(s) :TPS51220A
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