參數(shù)資料
型號(hào)： TPS40009DGQRG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 700 kHz SWITCHING FREQ-MAX, PDSO10
封裝： 3.05 X 4.98 MM, GREEN, PLASTIC, MSOP-10
文件頁(yè)數(shù)： 23/28頁(yè)
文件大小： 677K
代理商： TPS40009DGQRG4
TPS40007
TPS40009
SLUS589B NOVEMBER 2003 REVISED FEBRUARY 2005
4
www.ti.com
ELECTRICAL CHARACTERISTICS
temperature range, TA = 40_C to 85_C, VDD = 5.0 V, TA = TJ; all parameters measured at zero power dissipation
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DRIVER
RHDHI
HDRV pull-up resistance
VBOOTVSW = 3.3 V,
ISOURCE = 100 mA
3
5.5
RHDLO HDRV pull-down resistance
VBOOT VSW = 3.3 V,
ISINK = 100 mA
1.5
3
RLDHI
LDRV pull-up resistance
VDD = 3.3 V,
ISOURCE = 100 mA
3
5.5
RLDLO
LDRV pull-down resistance
VDD = 3.3 V,
ISINK = 100 mA
1.0
2.0
tRLD
LDRV rise time
15
35
tFLD
LDRV fall time
CLOAD = 1 nF
10
25
ns
tRHD
HDRV rise time
CLOAD = 1 nF
15
35
ns
tFHD
HDRV fall time
10
25
PREDICTIVE DELAY
VSWP
Sense threshold to modulate delay time
350
mV
TLDHD
Maximum delay modulation range time
LDRV OFF to HDRV ON
45
70
95
Predictive counter delay time per bit
LDRV OFF to HDRV ON
2.8
4.3
6.2
ns
THDLD
Maximum delay modulation range
HDRV OFF to LDRV ON
50
80
110
ns
Predictive counter delay time per bit
HDRV OFF to LDRV ON
3.0
4.8
6.6
SHUTDOWN
VSD
Shutdown threshold voltage
Outputs OFF
0.21
0.26
0.31
V
VEN
Device active threshold voltage
0.25
0.29
0.35
V
SOFTSTART
ISS
Soft-start source current
Outputs OFF
2.0
3.7
5.4
A
VSS
Soft-start voltage to begin VOUT start
0.35
0.65
0.95
V
BOOTSTRAP
RBOOT Bootstrap switch resistance
VDD = 3.3 V
50
100
RBOOT Bootstrap switch resistance
VDD = 5 V
35
70
VOUT PRE-BIAS
Recommended VOUT pre-bias level as
% of final regulation(1)(4)
FB percent of 700 mV
90%
SW NODE
ISW
Leakage current in shutdown
2
A
THERMAL SHUTDOWN
tSD
Shutdown temperature(1)
165
°C
Restart from thermal shutdown(1)
15
°C
(1)
Ensured by design. Not production tested.
(2)
Derate the maximum duty cycle by 3% for VDD < 3 V.
(3)
Operating at PWM on-times of less than 100 ns could lead to overlap between HDRV and LDRV pulses.
(4)
Prebiased output greater than 90% of final regulation may lead to sinking current from the prebias output.
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