參數(shù)資料
型號(hào)： TPS3106XXX
廠商： Texas Instruments, Inc.
英文描述： UltraLow Supply-Current/Supply-Voltage Supervisory Circuits
中文描述： 超低Supply-Current/Supply-Voltage監(jiān)控電路
文件頁(yè)數(shù)： 7/23頁(yè)
文件大小： 517K
代理商： TPS3106XXX
www.ti.com
PIN DESCRIPTIONS
(TOP VIEW)
RSTVDD
GND
MR
V
DD
SENSE
TPS3106
DBV PACKAGE
RSTSENSE
3
2
4
6
1
5
(TOP VIEW)
RESET
GND
MR
V
DD
PFI
TPS3103
DBV PACKAGE
PFO
3
2
4
6
1
5
(TOP VIEW)
RESET
GND
MR
V
DD
SENSE
TPS3110
DBV PACKAGE
WDI
3
2
4
6
1
5
TPS3103xxx
TPS3106xxx
TPS3110xxx
SLVS363E–AUGUST 2001–REVISED SEPTEMBER 2007
TERMINAL FUNCTIONS
TERMINAL
DEVICE
DESCRIPTION
NAME
GND
NO.
2
ALL
GND
Manual-reset input. Pull low to force a reset. RESET remains low as long as MR is low and for
the timeout period after MR goes high. Leave unconnected or connect to V
DD
when unused.
Power-fail input compares to 0.551 V with no additional delay. Connect to V
DD
if not used.
Power-fail output. Goes high when voltage at PFI rises above 0.551 V.
MR
ALL
3
PFI
PFO
TPS3103
TPS3103
TPS3103,
TPS3110
4
5
RESET
1
Active-low reset output. Either push-pull or open-drain output stage.
Active-low reset output. Logic level at RSTSENSE only depends on the voltage at SENSE and
the status of MR.
Active-low reset output. Logic level at RSTVDD only depends on the voltage at V
DD
and the
status of MR.
A reset will be asserted if the voltage at SENSE is lower than 0.551 V. Connect to V
DD
if
unused.
Supply voltage. Powers the device and monitors its own voltage.
Watchdog timer input. If WDI remains high or low longer than the time-out period, then reset is
triggered. The timer clears when reset is asserted or when WDI sees a rising edge or a falling
edge.
RSTSENSE
TPS3106
5
RSTVDD
TPS3106
1
TPS3106,
TPS3110
ALL
SENSE
4
V
DD
6
WDI
TPS3110
5
Copyright 2001–2007, Texas Instruments Incorporated
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