參數(shù)資料
型號： TPS3106XXX
廠商： Texas Instruments, Inc.
英文描述： UltraLow Supply-Current/Supply-Voltage Supervisory Circuits
中文描述： 超低Supply-Current/Supply-Voltage監(jiān)控電路
文件頁數(shù)： 4/23頁
文件大?。?/td> 517K
代理商： TPS3106XXX
www.ti.com
SWITCHING CHARACTERISTICS
At R
L
= 1 M
, C
L
= 50 pF, and T
A
= –40
°
C to +85
°
C, unless otherwise noted.
TIMING REQUIREMENTS
At R
L
= 1 M
, C
L
= 50 pF, and T
A
= –40
°
C to +85
°
C, unless otherwise noted.
TPS3103xxx
TPS3106xxx
TPS3110xxx
SLVS363E–AUGUST 2001–REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MR = 0 V, V
DD
= 3.3 V
SENSE, PFI, WDI = 0 V,
V
DD
= 3.3 V
MIN
–47
TYP
–33
MAX
–25
UNIT
μ
A
MR
SENSE, PFI,
WDI
I
IL
Low-level input current
–25
25
nA
High-level output current
at RESET
I
OH
Open-drain
V
DD
= V
IT
+ 0.2 V, V
OH
= 3.3 V
200
nA
V
DD
> V
IT
(average current),
V
DD
< 1.8 V
V
DD
> V
IT
(average current),
V
DD
> 1.8 V
V
DD
< V
IT
, V
DD
< 1.8 V
V
DD
< V
IT
, V
DD
> 1.8 V
1.2
3
2
4.5
I
DD
Supply current
μ
A
22
27
130
Internal pull-up resistor at MR
Input capacitance at MR, SENSE, PFI, WDI
70
100
k
pF
C
I
V
I
= 0 V to V
DD
1
(2)
Also refers to RSTVDD and RSTSENSE.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
D
Delay time
V
DD
≥
1.1
×
V
IT
, MR = 0.7
×
V
DD
, See
Timing Diagrams
65
130
195
ms
Propagation delay time,
high-to-low level output
V
to RESET or
RSTVDD delay
t
PHL
V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
40
μ
s
Propagation delay time,
low-to-high level output
V
to RESET or
RSTVDD delay
t
PLH
V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
40
μ
s
Propagation delay time,
high-to-low level output
SENSE to RESET or
RSTSENSE delay
t
PHL
V
DD
≥
0.8 V, V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
40
μ
s
Propagation delay time,
high-to-low level output
SENSE to RESET or
RSTSENSE delay
t
PLH
V
DD
≥
0.8 V, V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
40
μ
s
Propagation delay time,
high-to-low level output
t
PHL
PFI to PFO delay
V
DD
≥
0.8 V, V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
40
μ
s
Propagation delay time,
low-to-high level output
t
PLH
PFI to PFO delay
V
DD
≥
0.8 V, V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
300
μ
s
MR to RESET.
RSTVDD,
RSTSENSE delay
Propagation delay time,
low-to-high level output
t
PHL
V
DD
≥
1.1
×
V
IT
, V
IL
= 0.3
×
V
DD
, V
IH
= 0.7
×
V
DD
1
5
μ
s
MR to RESET.
RSTVDD,
RSTSENSE delay
Propagation delay time,
low-to-high level output
t
PLH
V
DD
≥
1.1
×
V
IT
, V
IL
= 0.3
×
V
DD
, V
IH
= 0.7
×
V
DD
1
5
μ
s
PARAMETER
Time-out period
TEST CONDITIONS
MIN
0.55
20
0.1
20
20
0.3
TYP
1.1
MAX
1.65
UNIT
s
t
T(OUT)
at WDI
at V
DD
at MR
at SENSE
at PFI
at WDI
V
DD
≥
0.85 V
V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT–
, V
IT–
= 0.86 V
V
DD
≥
V
IT
+ 0.2 V, V
IL
= 0.3
×
V
DD
, V
IH
= 0.7
×
V
DD
V
DD
≥
V
IT
, V
IH
= 1.1
×
V
IT
(S)
, V
IL
= 0.9
×
V
IT
(S)
V
DD
≥
0.85 V, V
IH
= 1.1
×
V
IT
(S)
,V
IL
= 0.9
×
V
IT
(S)
V
DD
≥
V
IT
, V
IL
= 0.3
×
V
DD
, V
IH
= 0.7
×
V
DD
t
W
Pulse width
μ
s
4
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Copyright 2001–2007, Texas Instruments Incorporated
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