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參數(shù)資料
| 型號： | TPS2383PMR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP64 |
| 封裝： | GREEN, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大小： | 397K |
| 代理商： | TPS2383PMR |
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TPS2383
SLUS559B APRIL 2003 REVISED JULY 2004
12
www.ti.com
FUNCTIONAL DESCRIPTION
SEPM STATE MACHINES
The TPS2383 has circuit resources that are common to each port and circuit resources that are shared by all
ports. Five independent state machines are used to control the common and shared PSEPM resources. Port
control, UV/OV/OC and overload protection are all features that are common to each port. Data acquisition and
power ramping are shared functions for all the ports.
The master sequencer state machine is used to index the port presently being serviced and to distribute the
shared resources to the currently selected port. The single master sequencer is responsible for incrementally
accessing ports 1 through 8 and allowing those ports to process register data when they are accessed. Ports
1 through 8 each have a port sequencer, which controls all the power enabling and fault protection functions
of the port per the register commands. The A/D has an A/D Sequencer that triggers, cycles and signals the port
and master sequencer upon completion. The ramp sequencer controls the power ramping resource and is
triggered by the port and master sequencer and provides a completion signal when power ramping is over.
Upon power-up the master sequencer is enabled and running after a POR delay and begins acting on register
commands. A shorter POR delay releases the reset on the I2C function and registers before the port reset is
removed. This arrangement allows for register setup and polling over the I2C bus quickly upon power up but
ensures that power cannot be applied until the power supply is fully energized and stable. The default power-up
state for all command registers is a null condition. The state sequence order of the TPS2383 is discovery,
classification and power delivery if a POE compliant device is detected on the other end of the data cable.
The master sequencer powers-up in a default free-running mode. The TPS2383 also has a JOG mode. By
setting the JOG_MODE register bit high, the master sequencer then no longer runs freely, but increments to
the next sequential port each time the JOG register bit is set to a logic 1. The JOG bit is self-cleared once the
port increments to the next position.
Sequencing starts with port 1 and ends with port 8 and then repeats. The port sequencer signals status
information to the master sequencer and skips over disabled ports. When the master sequencer detects an
enabled port, it pauses at that port until discovery, classification and power-up is complete before proceeding
to the next. When the master sequencer reaches a powered port, it pauses and take a reading of the ports
run-time current and/or voltage before proceeding to the next port. When a powered PD load is disconnected,
the disconnect event can be detected the next time that port is selected by the master sequencer. When the
disable bit of a powered port is set in the corresponding register, that operation is completed the next time the
master sequencer selects that port. An overcurrent fault event shuts down the offending port independent of
any sequencer state.
DUAL COLOR LED DRIVERS
The LED driver pins (L1 through L8) can be used to drive single or dual, color LEDs. These LEDs are intended
to provide installation or service personnel with the necessary information to install and troubleshoot the system
infrastructure. The Ln pins have internal tri-state drivers. These LEDs can be controlled directly from the I2C
registers. The reset state of all the LEDs is tri-state. Cross-conduction logic disables both internal high- and
low-side MOSFETS if an attempt is made to enable both transistors on a given port. These are high current
(10-mA) drivers that can be used for other applications such as the drive of optocouplers or electromechanical
devices, or can just be used as an 8-bit data port.
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