參數(shù)資料
型號: TPS2383PMR
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP64
封裝: GREEN, PLASTIC, LQFP-64
文件頁數(shù): 13/28頁
文件大小: 397K
代理商: TPS2383PMR
TPS2383
SLUS559B APRIL 2003 REVISED JULY 2004
20
www.ti.com
FUNCTIONAL DESCRIPTION
Table 9. Port Control
Write Register, Register Address = 010, Port Address = 011 (Port 4 Register)
BIT
FUNCTION
RANK
STATE
PRESET
STATE
D7
Port fault disable
Port
0
= Normal mode
1
= Disable the port overload and UV/OV timers
0
D6
Spare
0
D5
A/D input select
Common
0
= Normal mode select port currents
1
= Select port voltage
0
D4
LED blink enablle
Port
0
= LED is on continuous.
1
= Blink the enabled LED at a ”fast blink” rate. Note ”fast blink” rate (in
milliseconds) equivalent to 0.00013 x TPS2383 clock (CLK). This could be
as fast as 65ms for a 500 kHz TPS2383 clock.
0
D3
LED low-side enable
Port
1
= Enable the low-side FET and drive the LED pin low
0
D2
LED high-side enable
Port
1
= Enable the high-side FET and drive the LED pin to V5
0
D1
Enable modes
Port
00
= Port OFF or disable
01
= Discovery classification power on sequence
0
D0
Enable modes
Port
01
= Discovery classification power on sequence
10
= Sample powered-mode current
11
= Power-down an active port
0
Table 10. Port Control
Write Register, Register Address = 010, Port Address = 100111 (Port 5 through Port 8 Register)
BIT
FUNCTION
RANK
STATE
PRESET
STATE
D7
Port fault disable
Port
0
= Normal mode
1
= Disable the port overload and UV/OV timers
0
D6
Spare
0
D5
Spare
0
D4
LED blink enablle
Port
0
= LED is on continuous.
1
= Blink the enabled LED at a ”fast blink” rate. Note ”fast blink” rate (in
milliseconds) equivalent to 0.00013 x TPS2383 clock (CLK). This could be
as fast as 65ms for a 500 kHz TPS2383 clock.
0
D3
LED low-side enable
Port
1
= Enable the low-side FET and drive the LED pin low
0
D2
LED high-side enable
Port
1
= Enable the high-side FET and drive the LED pin to V5
0
D1
Enable modes
Port
00
= Port OFF or disable
01
= Discovery classification power on sequence
0
D0
Enable modes
Port
01
= Discovery classification power on sequence
10
= Sample powered-mode current
11
= Power-down an active port
0
Run Current/Voltage
During power delivery, the average value of the port running current or voltage is available from the read register.
The slope type converter used produces 12 bits of input offset corrected conversion with a typical integration
or averaging period of approximately one line cycle (16 ms). The actual averaging period is set by the CLK
frequency and is equivalent to 8192 periods of that frequency. The lower eight bits of this conversion are
available at the port register 011. The remaining upper four bits and A/D status bits are available at register 100.
The converter span is 4096 bits. The A/D conversion port displays the real time counter output and holds the
final static value at the completion of conversion
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