參數(shù)資料
型號(hào)： TPS2346PWRG4
廠商： Texas Instruments
文件頁(yè)數(shù)： 18/30頁(yè)
文件大?。?/td> 490K
描述： IC HOT SWAP POWER MGR 24-TSSOP
標(biāo)準(zhǔn)包裝： 2,000
類型： 熱交換控制器
應(yīng)用： 光纖學(xué)網(wǎng)絡(luò)（ONET）
內(nèi)部開關(guān)： 無(wú)
電源電壓： -5.2V，3.3V，5V，5.15V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
TPS2346
 
SLUS529  MAY 2002
18
www.ti.com
APPLICATION INFORMATION
The TPS2346 is shown in the typical application diagram being used in conjunction with a connector providing
three levels of pin staging. Although not an absolute requirement for device operation, pin staging provides
several benefits to the overall performance of the hot swap circuit. In order to use the precharge function
provided by the TPS2346, a minimum of two levels of staging is needed. The precharge supply is derived from
the 5-V supply input (VIN2); therefore, this supply must be present at some time before the boards bus lines
make contact with the backplane address/data bus in order to allow precharge before mating. A second benefit
of pin staging is it provides a mechanism for current-limited charging of the early power planes. Early power is
any plane which is on the unswitched side of the hot swap interface. Parasitic capacitance associated with the
interconnect system and the PCB planes, along with any bypass capacitance of the interface devices (e.g., the
hot swap controller, bus switches, the bridge device) appears on the input side of the connection hardware.
Therefore, it can still induce current spikes during hot swap even though the bulk capacitance is isolated. If
longer power pins are provided by the connector, they can be used for charging this smaller input capacitance
via simple resistive limiting. The resistors are subsequently bypassed when shorter power pins mate to establish
the low impedance power connection.
Finally, if a third level of staging is implemented, one of the shortest pins should be assigned to the ENABLE
input, as shown in the diagram. This helps ensure that all four supply voltages are stabilized at the controller
inputs before the ENABLE
can be asserted. It also allows this input to be grounded on the backplane in systems
not implementing individual slot control of plug-in electrical connection status.
Sense resistors R1 through R4 connect between the VINx and CSx pins of their respective supplies, and
provide load current magnitude information to the TPS2346. To turn on the negative voltage channel, the device
pulls the gate of MOSFET Q4 towards ground potential. Resistor R5 provides a gate pull down when the LCA
turns off, as the Channel 4 LCA does not drive to the negative rail.
Resistor R7 provides a pull-up on the ENABLE
 pin. This should be provided on-board, so that it is present
regardless of the connection status of this pin during hot swap events. Resistor R6 provides a pull-up on the
opendrain PG
 signal; a 10-k& resistor should suffice for this function. These two pull-ups are shown connected
to the early 5.15-V supply; they could conceivably be connected to any of the positive early plane voltages. For
most reliable operation, R7 should be connected to any of the earliest power pins, if pin timing is established
via a staged-pin connector; otherwise, it should be tied to VIN1 as shown.
A capacitor with a value between 0.1 礔 and 1 礔 (C3 in the diagram) is required between the CPUMP pin and
ground. This capacitor provides charge storage for the on-board charge pump. A 0.1-礔 ceramic is sufficient
for most applications.
ramp-up sequence
A successful ramp-up of the four back-end supplies consists of five pulses on the TPS2346 IRAMP pin. One
load voltage is ramped up during each of the first four IRAMP pulses. The fifth pulse enables the fault logic of
the last channel to turn on (Channel 4). This is shown graphically in Figure 19.
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