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參數(shù)資料
| 型號： | TPIC8101DWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封裝： | GREEN, PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 19/23頁 |
| 文件大?。?/td> | 511K |
| 代理商： | TPIC8101DWRG4 |
TPIC8101
KNOCK SENSOR INTERFACE
SLIS110A APRIL 2003 REVISED MAY 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
dc electrical characteristics, VDD = 5 V ±5%, input frequency before prescaler = 4 MHz to 20 MHz
(
±0.5%), TA = 40°C to 125°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
IDD(Q)
Quiescent current
VDD = 5 V
7.5
mA
IDD(OP)
Operating current
VDD = 5 V, XIN = 8 MHz
20
mA
Vmid0
Midpoint voltage
VDD = 5 V, ISource = 2 mA
2.3
2.5
2.55
V
Vmid1
Midpoint voltage
VDD = 5 V, ISink = 2 mA
2.4
2.5
2.7
V
Vmid2
Midpoint voltage
VDD = 5 V, IL = 0 mA
2.4
2.5
2.6
V
Rpull0
Internal pullup resistor CS, SDI, SCLK, TEST
VIN = GND
30
k
Rpull1
Internal pulldown resistor INT/HOLD
VIN = VDD
20
k
Ilkg
Input leakage current CS, SDI, SCLK,
INT/HOLD, TEST
Measured at GND and VDD,
VDD = 5.5 V = VIN
±3
A
VIL
Low-level input voltage INT/HOLD, CS,
TEST, SDI, SCLK
30% of
VDD
VIH
High-level input voltage INT/HOLD, CS,
TEST, SDI, SCLK
70% of
VDD
VOL
Low-level output voltage SDO
ISink = 4 mA, VDD = 5 V
0.7
V
VOH
High-level output voltage SDO
ISource = 100 A, VDD = 5 V
4.4
V
Ilkg(OL)
Low-level leakage current SDO
Measured at GND and VDD = 5 V,
SDO in high impedance
10
A
VOL(XOUT) Low-level output voltage
ISink = 500 A, VDD = 4.5 V
1.5
V
VOH(XOUT) High-level output voltage
ISource = 500 A, VDD = 5 V
4.4
V
Vhyst
Hysteresis voltage INT/HOLD, CS, XIN, SDI,
SCLK, TEST
0.4
V
Input Amplifiers
VOH(1)
CH1FB and CH2FB high-level output voltage
VDD = 5 V, ISource = 100 A
VDD –
0.05
VDD –
0.02
V
VOH(1)
CH1FB and CH2FB high-level output voltage
VDD = 5 V, ISource = 2 mA
VDD –
0.5
V
VOL(1)
CH1FB and CH2FB low-level output voltage
ISink = 100 A
15
50
mV
VOL(1)
CH1FB and CH2FB low-level output voltage
ISink = 2 mA
500
mV
CATTEN
Cross-coupling attenuation CH1FB and
CH2FB
fin max(ch1) = 20 kHz, measured on
channel 2
40
dB
Av
Open-loop gain
60
100
dB
GBW
Gain bandwidth product
Input range 0.5 V to 4.5 V
1
2.6
MHz
VIN
Input voltage range
0.05
VDD –
0.05
V
V(offset)
Offset voltage at input
10
mV
CMRR
Common-mode rejection ratio
Inputs at Vmid fin = 0 to 20 kHz
60
80
dB
PM
Phase margin
Gain = 1, CL = 200 pF, RL = 100 k
45
deg
Prescaler, XIN
VOSC
Minimum input peak amplitude(1)
VDD = Vmin, oscillator inverter biased
feedback resistor 1 M
, fosc = 24 MHz
150
mV
CIN
Input capacitance
Assured by design
7
pF
Ilkg(XIN)
Leakage current
1
A
NOTE 1: 150-mV input amplitude on the 4-MHz clock input only applies if the feedback network is completed. Without the feedback network, the
4-MHz signal should be at 05V levels.
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