參數(shù)資料
型號(hào)： TPIC43T01DA
廠商： Texas Instruments, Inc.
英文描述： THREE-PHASE BRUSHLESS MOTOR RPM CONTROLLERS
中文描述： 三相無(wú)刷電機(jī)轉(zhuǎn)速控制器
文件頁(yè)數(shù)： 12/27頁(yè)
文件大?。?/td> 376K
代理商： TPIC43T01DA
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPMCONTROLLERS
SLIS098 – APRIL 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
lock timer oscillator/counter
Overall lock timer functionality is implemented by the combination of the oscillator and counter. The lock timer
oscillator is identical to the sampling frequency oscillator. The external resistor (RT) is used as the current
setting reference for both blocks. An external capacitor must be connected from the CLT terminal to GND to
set the period, T
(CLT)
, of the lock timer oscillator. The nominal period is determined by the formula:
T
CLT
= 2
×
RT
×
CLT. When an out-of-lock signal is generated by the lock detect block (see ock detect section),
the lock timer counter will count at the frequency of the lock timer oscillator. Should the out-of-lock signal remain
for the duration of the counter completing 1023 counts, a lock timer time-out signal will then be generated which
the shutdown logic block will respond to (see shutdown section). The lock timer time-out is thus set by
T
CLT
×
1023.
power-up clear
An under-voltage lockout and power-up clear are provided to ensure FET drive outputs are set to a known state
during power-up. The device is held in a CLEAR state until the following three conditions are met:
1.
V
DD
> V
DD(uvlo)
, after which a power-up clear (PUC) time will begin.
The PUC timer counts 3 cycles of internal 20 kHz signal (internal 5.8 MHz
÷
255), or
132
μ
s.
2.
3.
The charge pump voltage, V
(CP)
, has charged to at least V
CC
+ 5 V.
shutdown
The scheme for shutdown includes monitoring two conditions and latching the device in a CLEAR state should
an abnormal condition occur. Once shutdown is latched, the S/S input must be cycled high then low, or power
cycled OFF then ON to release shutdown and resume normal operation. If an abnormal condition still exists after
the S/S pin has been cycled, the device will relatch shutdown. A 1 on either S/S or V
DD
pins will clear the lock
timer. A V
DD
under-voltage-lockout detect will force a global clear. (see Table 2 and Figure 6).
Table 2. Shutdown Conditions
LATCHED SHUTDOWN
CONDITIONS
UNLATCHED SHUTDOWN CONDITIONS
S/S
INTERNAL
CLR
LT
LTCLR
GATE
OUTPUTS
OCSD
LT
CP UV
VDD UVLO
X
INPUT
X
X
X
H
0
0
0
X
X
X
VDD < VDD(uvlo)
X
0
0
0
V(SENSE) < V(OCSD)
Out of
Lock < t(LT)
VO(CP) > V(CPUV)
VDD > VDD(uvlo) + 3 counts
H
↓
L
1
1
1
X
X
VCP < V(CPUV)
for > t(DG)
X
X
X
X
0
V(SENSE) > V(OCSD)
for > t(DG)
X
X
X
X
X
X
0
X
Out of
Lock > t(LT)
X
X
L
X
1
0
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