參數(shù)資料
型號(hào): TPIC43T01
廠商: Texas Instruments, Inc.
英文描述: Three-Phase Brushless Motor RPM Controller
中文描述: 三相無(wú)刷電機(jī) RPM 控制器
文件頁(yè)數(shù): 22/27頁(yè)
文件大?。?/td> 376K
代理商: TPIC43T01
TPIC43T01, TPIC43T02
THREE-PHASE BRUSHLESS MOTOR RPMCONTROLLERS
SLIS098 – APRIL 2000
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
EEPROM registers
There are two user configurable EEPROM bit registers accessible through the serial test interface when the
device is configured in TEST mode. This mode is enabled when the TEST pin is held high at 5 V. Once the device
is placed in TEST mode, either register can be programmed by transmitting a 16-bit word. The first three bits
of this transmission are the address and R/W for the register the user wishes to modify. The next five bits must
be held low, and the remaining eight bits are configuration bits. Each register must be programmed
independently, i.e. once the register value is written, the V
PP
pin must immediately be taken to 13.5 V in the
manner described in the EEPROM Programmingsection. The two EEPROM registers are summarized in
Table 7. A detailed definition outlining the function of each bit in the EEPROM is presented in the respective
functional description sections of this specification (see Notes 5 and 6).
Table 7. EEPROM Register Definition
ADDR
EEPROM REGISTER CONFIGURATION BITS
BIT 5
BIT 4
BIT 7
BIT 6
BIT 3
BIT 2
BIT 1
BIT 0
0
K2 Coefficient
Coast Enable
Synchronous
Rectification
Integrator Gain Select
TPIC43T01 default
1
0
0
1
1
0
0
0
TPIC43T02 default
1
0
0
1
0
0
0
0
1
K1 Coefficient
FG Frequency Select
TPIC43T01 default
0
1
1
1
0
0
1
1
TPIC43T02 default
NOTES:
5. Bit 0 in the EEPROM register definition table corresponds to D0 and E0 in the serial protocol sequence.
6. Data read out of the EEPROM corresponds to the contents of the register at the time it is read. (A register can
be read after programming it in order to verify that the EEPROM was programmed properly.)
0
1
1
1
0
0
1
1
serial test interface
User-programmable functions are controlled using two 16-bit EEPROM registers. These registers are
programmed by placing the device in program/test mode by pulling the TEST pin high and transferring data
using the serial interface. Pins 14 and 17–19 are multipurpose pins, which are configured for serial test mode
when the TEST pin is high (see Table 8).
Table 8. Serial Test Interface Pin Definition
PIN
PIN DESCRIPTION
NAME
NO.
SO
14
Serial data output. SO is an output terminal that reads data from the EEPROM.
SCLK
17
Serial clock. SCLK clocks the shift register. Serial data is clocked into the serial data input (SI) port on the rising edge of the
serial clock. Serial output data is clocked out of the serial data output (SO) port on the rising edge of the serial clock.
SIENB
18
Serial transfer enable. A low to high transition on the SIENB pin enables the serial interface to send or receive data (see Figure
2). The SIENB signal must be taken low after 16 bits of data has been transferred to insure data has been loaded into the proper
bit locations. During program mode, the VPP input is strobed after SIENB is taken low to program the EEPROM.
Serial input. SI is an input terminal to load the EEPROM input register.
SI
19
VPP
TEST
35
EEPROM program voltage. VPP transfers data from the EEPROM input register to the respective address location.
Serial interface/test mode enable. TEST is taken high to enable the serial interface.
36
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