
ABSOLUTE MAXIMUM RATINGS
TYPICAL DISSIPATION RATINGS
TPA3100D2-Q1
SLOS557 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 85°C
QFN – RGZ
Reel of 2500
TPA3100D2IRGZRQ1
TPA3100D2I
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
(2)
over operating free-air temperature range (unless otherwise noted)
(1)
VCC
Supply voltage range
AVCC, PVCC
–0.3 V to 30 V
SHUTDOWN, MUTE
–0.3 V to VCC + 0.3 V
VI
Input voltage range
GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV,
–0.3 V to VREG + 0.5 V
SYNC
Continuous total power dissipation
See Dissipation Ratings Table
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Operating junction temperature range(2)
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
RLoad
Load resistance
3.2
Minimum
Human-Body Model (3) (all pins)
2 kV
Electrostatic discharge
Machine Model (4) (all pins)
150 V
Charged-Device Model (5) (all pins)
750 V
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The TPA3100D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Brief
SLMA002 for more information about using the thermal pad.
(3)
In accordance with AEC Q100, Test method Q100-002
(4)
In accordance with AEC Q100, Test method Q100-003
(5)
In accordance with AEC Q100, Test method Q100-011
POWER RATING
DERATING FACTOR
POWER RATING
PACKAGE
TA ≤ 25°C
TA > 25°C
TA = 70°C
TA = 85°C
48-pin RGZ (QFN)
4.63 W
37 mW/°C(1)
2.96 W
2.41 W
(1)
This data was taken using 1-oz trace and copper pad that is soldered directly to a JEDEC standard high-K PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Brief
SLMA002 for more information about using the thermal
pad.
2
Copyright 2008, Texas Instruments Incorporated