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參數(shù)資料
| 型號： | TP3420AN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ISDN S/T Interface Device |
| 中文描述： | DATACOM, DIGITAL SLIC, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 3/32頁 |
| 文件大?。?/td> | 524K |
| 代理商： | TP3420AN |
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Pin Descriptions
(Continued)
Name
FS
a
Description
In NT modes and TES mode, this pin is
the Transmit Frame Sync pulse
TTL/CMOS input, requiring a positive
edge to indicate the start of the active
channel time for transmit “B” and “D”
channel data into B
x
. In TEM mode only,
this pin is a digital output pulse whose
positive indicates the start of the “B”
channel data transfer at both B
x
and B
r
.
In NT modes and TES mode, this pin is
the Receive Frame Sync pulse
TTL/CMOS input, requiring a positive
edge to indicate the start of the active
channel time of the device for receive “B”
and “D” channel data out from B
r
. In TEM
mode only, when digital interface Format
1 is selected, this pin is an 8-bit wide
pulse which indicates the active slot for
the B2 channel on the digital interface.
The DCKE command will alter the
function of this pin. See Table 2 for
details.
TTL/CMOS input for “B” and “D” channel
data to be transmitted to the line; must be
synchronous with BCLK.
CMOS output for “B” and “D” channel
data received from the line, which is
synchronous with BCLK. When not
shifting data, this pin is TRI-STATE
.
In TEM mode, this pin by default is a
CMOS output which is normally low and
pulses high to indicate the active bit-times
for “D” channel Transmit data at the B
x
input. It is intended to be gated with
BCLK to control the shifting of data from
layer 2 device to the TP3420A transmit
buffer.
In NT modes, this pin by default is a
pulse output (DEN
x
) which occurs in
every 8 KHz frame and indicates the
location of D channel data input on the B
x
pin.
In TES mode, this pin by default is an
output synchronized clock (SCLK) at the
frequency selected by the Digital
Interface Format. This clock is
phase-locked to the received line signal,
and is intended to be used as the BCLK
source.
This pin called P2 in Table 1 can also be
programmed to provide alternate
functions. See Table 1 for details.
MICROWIRE control channel serial data
TTL/CMOS input.
FS
b
(Pin 11)
B
x
B
r
DEN
x
/p2
(Pin 8)
CI
Name
CO
Description
Control channel serial data CMOS output
for status information. When not enabled
by CS, this output is TRI-STATE.
TTL/CMOS clock input for the Control
Channel.
Chip Select input which enables the
control channel data to be shifted in and
out when pulled low. When high, this pin
inhibits the Control interface.
Interrupt output, a latched n-channel
open-drain output signal which is
normally high impedance, and goes low
to indicate a change of status of the loop
transmission system.
In all modes, this pin by default is the
Line Signal Detect output, an n-channel
open-drain output which is normally
high-impedance, but pulls low when the
device is powered down and a received
line signal is detected. It is intended to be
used to “wake-up” a microprocessor from
a low-power idle mode. This output is
high impedance when the device is
powered up.
This pin P1 in Table 1 can also be
programmed to provide alternate
functions. See Table 1 for details.
Transmit AMI signal differential outputs to
the line transformer. When used with a
2:1 step-down transformer, the line signal
conforms to the output pulse masks in
I.430.
Receive AMI signal differential inputs
from the line transformer. The L
i
pin is
also the internal voltage reference pin,
and must be decoupled to GND with a 10
μf capacitor in parallel with a 0.1 μF
ceramic capacitor.
CCLK
CS
INT
LSD/P1
(Pin 18)
L
o
+, L
o
L
i
+, L
i
Note 1:
Crystal specification: 15.36 MHz parallel resonant; R
s
≤
150
,
C
L
= 20 pF and C
O
<
7 pF.
Note 2:
The 33 pF includes any board capacitance.
ALTERNATE PIN FUNCTIONS
With a MICROWIRE command PINDEF (B'1110 0 x2 x1 x0)
the pin signal functions of these pins can be changed to pro-
vide alternate functions (see Table 1 and the MICROWIRE
command in Table 4). “
*
” indicates the default pin function af-
ter a device mode selection. Power-up default device mode
is NTA.
www.national.com
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3420AV | ISDN S/T Interface Device |
| TP3464 | MICROWIRE⑩ Interface Device (MID) |
| TP3464N | MICROWIRE⑩ Interface Device (MID) |
| TP3465N | MICROWIRE⑩ Interface Device (MID) |
| TP3465V | MICROWIRE⑩ Interface Device (MID) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3420AN308 | 功能描述:IC INTERFACE DEVICE ISDN 20-DIP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:* 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| TP3420AV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:ISDN S/T Interface Device |
| TP3420AV308 | 功能描述:射頻收發(fā)器 RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TP3420AV308/63 | 功能描述:射頻收發(fā)器 RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TP3420AV308/63SN | 功能描述:射頻收發(fā)器 RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
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