參數(shù)資料
型號(hào)： TP3420A
廠商： National Semiconductor Corporation
英文描述： ISDN S/T Interface Device
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)的S / T接口設(shè)備
文件頁數(shù)： 24/32頁
文件大小： 524K
代理商： TP3420A
Absolute Maximum Ratings
(Note 24)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
CC
to GND
Voltage at L
i
, L
0
Voltage at any Digital Input
7V
V
CC
+1V to GND 1V
V
CC
+1V to GND 1V
Storage Temperature Range
Current at L
0
Current at any Digital Output
Lead Temperature
(Soldering, 10 sec.)
ESD rating
65C to+150C
±
100 mA
±
50 mA
300C
2000V
Electrical Characteristics
Unless otherwise noted: limits printed in
bold
characters are electrical testing limits at V
= 5.0V and T
= 25C. All other
limits are design goals for V
= 5.0V
±
5%, and T
= 0C to 70C. This data sheet is still preliminary and parameter limits
are subject to change based on further characterization testing.
Symbol
Parameter
Conditions
Limits
Units
Min
Typ
Max
DIGITAL INTERFACES
V
IL
Input Low Voltage
V
IH
Input High Voltage
V
ILX
Input Low Voltage
V
IHX
Input High Voltage
V
OL
Output Low Voltage
All Digital Inputs
All Digital Inputs
MCLK/XTAL Input
MCLK/XTAL Input
B
r
, I
L
= 3.2 mA
All Other Digital Outputs, I
L
= 1 mA
B
r
, I
L
= 3.2 mA
All Other Digital Outputs, I
L
= 1 mA
All Outputs, I
L
= 100 μA
Any Digital Input, GND
<
V
IN
<
V
CC
B
r
, INT, LSD, CO
GND
<
V
OUT
<
V
CC
0.7
V
V
V
V
V
2.2
0.5
V
CC
0.5
0.4
V
OH
Output High Voltage
2.4
2.4
V
V
V
μA
μA
V
CC
0.5
10
10
I
I
I
OZ
Input Current
Output Current in High
Impedance State
(TRI-STATE)
LINE INTERFACES
R
Li
Differential Input
Resistance
CL
L0
Load Capacitance
POWER DISSIPATION
I
CC
0
Power Down Current
I
CC
1
Power Up Current
TRANSMISSION PERFORMANCE
Transmit Pulse Amplitude
Transmit Pulse Unbalance
Input Pulse Amplitude
Output Impedance when
Transmitting Binary Zeroes
10
10
GND
<
L
i
+, L
i
<
V
CC
200
k
Between L
o
+ and L
o
200
pF
All Outputs Open-Circuit
As Above, Device Deactivated (Note 25)
1.20
25
mA
mA
R
L
= 270
Between L
o
+ and L
o
(Note 26)
0+ Relative to 0
Differential Between L
i
+ and L
i
50
Load
400
Load (Note 27)
±
1.90
±
2.14
±
5
Vpk
%
mVpk
±
175
100
14
Note 24:
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 25:
When the device is activated and driving a correctly terminated line, I
CC1
increases by several mA. A worst-case data pattern, consisting of all binary 0’s,
increases I
CC1
by approximately 8 mA.
Note 26:
The pulse amplitude at the L
o
±
pins allows for approximately 1 dB transformer insertion loss to meet the 0.75V pulse mask test when the line is terminated
in 50
.
Note 27:
Using a 2:1 PE64995 transformer and a connecting cord. See AN-872 (TP3420A Line Interface or Circuit Considerations) for more details.
www.national.com
24
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