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參數(shù)資料
| 型號(hào)： | TP3404 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Quad Digital Adapter for Subscriber Loops (QDASL) |
| 中文描述： | 四適配器數(shù)字用戶環(huán)路（QDASL） |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 212K |
| 代理商： | TP3404 |
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Electrical Characteristics
Unless otherwise specified, limits printed in
BOLD
characters are guaranteed for
V
CCA
e
V
CCD
e
5V
g
5%, T
A
e
0
§
C to
a
70
§
C. Typical characteristics are specified at V
DDA
e
V
DDD
e
5.0V, T
A
e
25
§
C. All
signals are referenced to GND, which is the common of GNDA and GNDD (Continued)
TIMING SPECIFICATIONS
(Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INTERFACE TIMING
f
BCLK
BCLK Frequency
4.096
4.1
MHz
t
WBH
,
t
WBL
Clock Pulse Width High
and Low for BCLK
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
70
70
ns
t
RB
,
t
FB
Rise Time and Fall Time
of BCLK
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
15
15
ns
t
HBM
BCLK Transition to MCLK High or Low
b
30
30
ns
t
SFC
Set up Time, FS Valid to BCLK Invalid
20
4
ns
t
HCF
Hold Time, BCLK Low to FS Invalid
40
30
ns
t
SBC
Setup Time, BI Valid to BCLK Invalid
30
11
ns
t
HCB
Hold Time, BCLK Valid to BI Invalid
40
7
ns
t
SDC
Setup Time, DI Valid to BCLK Low
30
ns
t
HCD
Hold Time, BCLK Low to DI Invalid
40
ns
t
DCB
Delay Time, BCLK High to BO Valid
Load
e
2 LSTTL
a
100 pF
80
ns
t
DCBZ
Delay Time, BCLK Low to BO High-Z
80
120
ns
t
DCD
Delay Time, BCLK High to DO valid
Load
e
2 LSTTL
a
100 pF
80
ns
t
DCZ
Delay Time, BCLK Low to DO High
Impedance
40
120
ns
t
DCT
Delay Time, BCLK High to TSB Low
120
ns
t
ZBT
Disable Time, BCLK Low to TSB High-Z
120
ns
MICROWIRE CONTROL INTERFACE TIMING
f
CCLK
Frequency of CCLK
2.1
MHz
t
CH
Period of CCLK High
Measured from V
IH
to V
IH
150
ns
t
CL
Period of CCLK Low
Measured from V
IL
to V
IL
150
ns
t
SSC
Setup Time, CS Low to CCLK High
50
ns
t
HCS
Hold Time, CCLK High to CS Transition
40
ns
t
SIC
Setup Time, CI Valid to CCLK High
50
ns
t
HCI
Hold Time, CCLK High to CI Invalid
20
ns
t
DCO
Delay Time, CCLK Low to CO Valid
80
ns
t
DSOZ
Delay Time, CS High to CO High-Z
80
ns
t
DCIZ
Delay Time, CCLK to INT High-Z
100
ns
Notes:
For the purposes of this specification the following conditions apply
a. All input signals are defined as V
IL
e
0.4V, V
IH
e
2.7V, t
r
k
10 ns, t
f
k
10 ns.
b. Delay times are measured from the input signal Valid to the output signal Valid.
c. Setup times are measured from the Data input Valid to the clock input Invalid.
d. Hold times are measured from the clock signal Valid to the Data input Invalid.
3
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