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參數(shù)資料
| 型號： | TP3155N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TP3155 Time Slot Assignment Circuit |
| 中文描述： | DATACOM, TIME SLOT ASSIGNER, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 208K |
| 代理商： | TP3155N |
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
V
CC
Relative to GND
Voltage at Any Input
or Output
7V
V
CC
a
0.3V to GND
b
0.3V
Operating Temperature Range
(Ambient)
b
25
§
C to
a
125
§
C
Storage Temperature Range
(Ambient)
b
65
§
C to
a
150
§
C
Maximum Lead Temperature
(Soldering, 10 seconds)
300
§
C
ESD rating to be determined.
DC Electrical Characteristics
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
CC
e
5.0V
g
5%; T
A
e
0
§
C to
a
70
§
C by
correlation with 100% electrical testing at T
A
e
25
§
C. All other limits are assured by correlation with other production tests and/
or product design and characterization. Typicals specified at V
CC
e
5.0V, T
A
e
25
§
C.
Parameter
Conditions
Min
Typ
Max
Units
Input Voltage Levels
V
IH
, Logic High
V
IL
, Logic Low
2.0
V
V
0.7
Input Currents
All Inputs Except MODE
MODE
V
IL
k
V
IN
k
V
IH
V
IN
e
0V
b
1
b
100
1
m
A
m
A
Output Voltage Levels
V
OH
, Logic High
V
OL
, Logic Low
FS
X
and FS
R
Outputs, I
OH
e
3 mA
FS
X
and FS
R
Outputs, I
OL
e
5 mA
TS
X
Output, I
OL
e
5 mA
2.4
V
V
V
0.4
0.4
Power Dissipation
Operating Current
BCLK
e
2.048 MHz,
All Outputs Open-Circuit
1
1.5
mA
Timing Specifications
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
CC
e
5.0V
g
5%, T
A
e
0
§
C to
a
70
§
C by
correlation with 100% electrical testing at T
A
e
25
§
C. All other limits are assured by correlation with other production tests and/
or product design and characterization. Typicals specified at V
CC
e
5.0V, T
A
e
25
§
C. All timing parameters are measured at
V
OH
e
2.0V and V
OL
e
0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol
Parameter
Conditions
Min
Max
Units
t
PC
Period of Clock
BCLK, CLK
C
480
ns
t
WCH
Width of Clock High
BCLK, CLK
C
160
ns
t
WCL
Width of Clock Low
BCLK, CLK
C
160
ns
t
SDC
Set-Up Time from D
C
to CLK
C
50
ns
t
HCD
Hold Time from CLK
C
to D
C
50
ns
t
SCC
Set-Up Time from CS to CLK
C
30
ns
t
HCC
Hold Time from CLK
C
to CS
100
ns
t
SCHC
Set-Up Time from Channel Select to CLK
C
50
ns
t
HCHC
Hold Time from Channel Select to CLK
C
50
ns
t
DBF
Delay Time from BCLK Low to FS
X/R
0–3
High or Low
C
L
e
50 pF
100
ns
t
HSYNC
Hold Time from BCLK to Frame Sync
50
ns
t
SSYNC
Set-Up Time from Frame Sync to BCLK
100
ns
t
DTL
Delay to TS
X
Low
C
L
e
50 pF
R
L
e
1k to V
CC
140
ns
t
DTH
Delay to TS
X
High
30
140
ns
t
RC
, t
FC
Rise and Fall Time of Clock
BCLK, CLK
C
50
ns
2
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