參數(shù)資料
型號: TP3076
廠商: National Semiconductor Corporation
元件分類: Codec
英文描述: COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications
中文描述: 組合二可編程PCM編解碼器/濾波器ISDN和數(shù)字電話應(yīng)用
文件頁數(shù): 5/18頁
文件大?。?/td> 222K
代理商: TP3076
Programmable Functions
(Continued)
Coding Law Selection
Bits “MA” and “IA” in Table 2 permit the selection of μ255
coding or A-law coding, with or without even bit inversion.
Analog Loopback
Analog Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in Table 2 In the
analog loopback mode, the Transmit input VF
I is isolated
from the input pin and internally connected to the VF
O out-
put, forming a loop from the Receive PCM Register back to
the Transmit PCM Register. The VF
O pin remains active,
and the programmed settings of the Transmit and Receive
gains remain unchanged, thus care must be taken to ensure
that overload levels are not exceeded anywhere in the loop.
Digital Loopback
Digital Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in Table 2 This
mode provides another stage of path verification by enabling
data written into the Receive PCM Register to be read back
from that register in any Transmit time-slot at D
1. PCM de-
coding continues and analog output appears at VF
0. The
output can be disabled by programming ‘No Output’ in the
Receive Gain Register (see Table 8).
INTERFACE LATCH DIRECTIONS
Immediately following power-on, all Interface Latches as-
sume they are inputs, and therefore all IL pins are in a high
impedance state. Each IL pin may be individually pro-
grammed as a logic input or output by writing the appropriate
instruction to the LDR, see Table 1 and Table 3 For mini-
mum power dissipation, unconnected latch pins should be
programmed as outputs. For the TP3076, bits 2 and 3 should
always be programmed as “1” (outputs).
Bits L
–L
must be set by writing the specific instruction to
the LDR with the L bits in the second byte set as follows:
TABLE 3. Byte 2 Functions of Latch Direction Register
Byte 2 Bit Number
4
L
3
7
L
0
6
L
1
5
L
2
3
1
2
1
1
X
0
X
L
n
Bit
0
1
IL Direction
Input
Output
X = Don’t Care
INTERFACE LATCH STATES
Interface Latches configured as outputs assume the state
determined by the appropriate data bit in the 2-byte instruc-
tion written to the Interface Latch Register (ILR) as shown in
Table 1 and Table 4 Latches configured as inputs will sense
the state applied by an external source, such as the
Off-Hook detect output of a SLIC. All bits of the ILR, i.e.
sensed inputs and the programmed state of outputs, can be
read back in the 2nd byte of a READ from the ILR.
It is recommended that during initialization, the state of IL
pins to be configured as outputs should be programmed first
followed immediately by the Latch Direction Register.
TABLE 4. Interface Latch Data Bit Order
Bit Number
4
D
3
7
6
5
3
2
1
X
0
X
D
0
D
1
D
2
D
4
D
5
TABLE 5. Coding Law Conventions
μ255 Law
True A-Law with
Even Bit Inversion
MSB
1 0 1 0 1 0 1 0
1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 0 1 0 1 0 1 0
A-Law without
Even Bit Inversion
MSB
1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1
MSB
1 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
LSB
LSB
LSB
V
IN
= +Full Scale
V
IN
= 0V
V
IN
= Full Scale
Note 5:
The MSB is always the first PCM bit shifted in or out of COMBO II.
www.national.com
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