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參數(shù)資料
| 型號： | TP3067V |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Solid-State Timer; Supply Voltage Max:120VAC; Time Range Max:30s; Time Range Min:3s; Output Current:5A; Supply Voltage Min:100VAC; Switch Function:DPDT RoHS Compliant: Yes |
| 中文描述： | A-LAW, PCM CODEC, PQCC20 |
| 封裝： | PLASTIC, CC-20 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 276K |
| 代理商： | TP3067V |
Functional Description
(Continued)
table of Transmission Characteristics). The FS
X
frame sync
pulse controls the sampling of the filter output, and then the
successive-approximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out through D
X
at the next FS
X
pulse. The total encoding delay will be ap-
proximately 165
m
s (due to the transmit filter) plus 125
m
s
(due to encoding delay), which totals 290
m
s. Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration.
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz. The decoder is A-law (TP3067) or
m
-law (TP3064) and the 5th order low pass filter corrects for
the sin x/x attenuation due to the 8 kHz sample/hold. The
filter is then followed by a 2nd order RC active post-filter
with its output at VF
R
O. The receive section is unity-gain,
but gain can be added by using the power amplifiers. Upon
the occurrence of FS
R
, the data at the D
R
input is clocked in
on the falling edge of the next eight BCLK
R
(BCLK
X
) peri-
ods. At the end of the decoder time slot, the decoding cycle
begins, and 10
m
s later the decoder DAC output is updated.
The total decoder delay is
E
10
m
s (decoder update) plus
110
m
s (filter delay) plus 62.5
m
s (
(/2
frame), which gives
approximately 180
m
s.
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided for direct-
ly driving a matched line interface transformer. The gain of
the first power amplifier can be adjusted to boost the
g
2.5V
peak output signal from the receive filter up to
g
3.3V peak
into an unbalanced 300
X
load, or
g
4.0V into an unbal-
anced 15 k
X
load. The second power amplifier is internally
connected in unity-gain inverting mode to give 6 dB of signal
gain for balanced loads.
Maximum power transfer to a 600
X
subscriber line termina-
tion is obtained by differentially driving a balanced trans-
former with a
S
2:1 turns ratio, as shown inFigure 4. A total
peak power of 15.6 dBm can be delivered to the load plus
termination.
ENCODING FORMAT AT D
X
OUTPUT
TP3064
m
-Law
TP3067
A-Law
(Includes Even Bit Inversion)
V
IN
e a
Full-Scale
V
IN
e
0V
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
D
0
V
IN
e b
Full-Scale
0
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3067V/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC |
| TP3067V/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC |
| TP3067V/NOPB | 功能描述:IC INTERFACE ENHANCED SER 20PLCC RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| TP3067V-X | 功能描述:IC INTERFACE ENHANCED SER 20PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| TP3067WM | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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