參數(shù)資料
型號(hào)： TP3064WM
廠(chǎng)商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 編解碼器
英文描述： ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO
中文描述： MU-LAW, PCM CODEC, PDSO20
封裝： 0.300 INCH, PLASTIC, SO-20
文件頁(yè)數(shù)： 3/18頁(yè)
文件大小： 276K
代理商： TP3064WM
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initializ-
es the COMBO
TM
and places it into a power-down state. All
non-essential circuits are deactivated and the D
X
, VF
R
O,
VPO
b
and VPO
a
outputs are put in high impedance states.
To power-up the device, a logical low level or clock must be
applied to the MCLK
R
/PDN pinand FS
X
and/or FS
R
pulses
must be present. Thus, 2 power-down control modes are
available. The first is to pull the MCLK
R
/PDN pin high; the
alternative is to hold both FS
X
and FS
R
inputs continuously
lowDthe device will power-down approximately 2 ms after
the last FS
X
or FS
R
pulse. Power-up will occur on the first
FS
X
or FS
R
pulse. The TRI-STATE PCM data output, D
X
,
will remain in the high impedance state until the second FS
X
pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive di-
rections. In this mode, a clock must be applied to MCLK
X
and the MCLK
R
/PDN pin can be used as a power-down
control. A low level on MCLK
R
/PDN powers up the device
and a high level powers down the device. In either case,
MCLK
X
will be selected as the master clock for both the
transmit and receive circuits. A bit clock must also be ap-
plied to BCLK
X
and the BCLK
R
/CLKSEL can be used to
select the proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation,
the device automatically compensates for the 193rd clock
pulse each frame.
With a fixed level on the BCLK
R
/CLKSEL pin, BLCK
X
will be
selected as the bit clock for both the transmit and receive
directions. Table I indicates the frequencies of operation
which can be selected, depending on the state of BCLK
R
/
CLKSEL. In this synchronous mode, the bit clock, BCLK
X
,
may be from 64 kHz to 2.048 MHz, but must be synchro-
nous with MCLK
X
.
Each FS
X
pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled D
X
output on the positive edge of BCLK
X
. After 8
bit clock periods, the TRI-STATE D
X
output is returned to a
high impedance state. With an FS
R
pulse, PCM data is
latched via the D
R
input on the negative edge of BCLK
X
(or
BCLK
R
if running). FS
X
and FS
R
must be synchronous with
MCLK
X/R
.
TABLE I. Selection of Master Clock Frequencies
Master Clock
Frequency Selected
BCLK
R
/CLKSEL
TP3067
TP3064
Clocked
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
0
1.536 MHz or
1.544 MHz
2.048 MHz
1
1.536 MHz or
1.544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK
X
and MCLK
R
must be 2.048
MHz for the TP3067, or 1.536 MHZ, 1.544 MHz for the
TP3064, and need not be synchronous. For best transmis-
sion performance, however, MCLK
R
should be synchronous
with MCLK
X
, which is easily achieved by applying only static
logic levels to the MCLK
R
/PDN pin. This will automatically
connect MCLK
X
to all internal MCLK
R
functions (see Pin
Description). For 1.544 MHz operation, the device automati-
cally compensates for the 193rd clock pulse each frame.
FS
X
starts each encoding cycle and must be synchronous
with MCLK
X
and BCLK
X
. FS
R
starts each decoding cycle
and must be synchronous with BCLK
R
. BCLK
R
must be a
clock, the logic levels shown in Table I are not valid in asyn-
chronous mode. BCLK
X
and BCLK
R
may operate from 64
kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse (the
same as the TP3020/21 CODECs) or a long frame sync
pulse. Upon power initialization, the device assumes a short
frame mode. In this mode, both frame sync pulses, FS
X
and
FS
R
, must be one bit clock period long, with timing relation-
ships specified in Figure 2. With FS
X
high during a falling
edge of BCLK
X
, the next rising edge of BCLK
X
enables the
D
X
TRI-STATE output buffer, which will output the sign bit.
The following seven rising edges clock out the remaining
seven bits, and the next falling edge disables the D
X
output.
With FS
R
high during a falling edge of BCLK
R
(BCLK
X
in
synchronous mode), the next falling edge of BCLK
R
latches
in the sign bit. The following seven falling edges latch in the
seven remaining bits. All devices may utilize the short frame
sync pulse in synchronous or asynchronous operating
mode.
LONG FRAME SYNC OPERATION
To use the long (TP5116A/56 CODECs) frame mode, both
the frame sync pulses, FS
X
and FS
R
, must be three or more
bit clock periods long, with timing relationships specified in
Figure 3. Based on the transmit frame sync, FS
X
, the COM-
BO will sense whether short or long frame sync pulses are
being used. For 64 kHz operation, the frame sync pulse
must be kept low for a minimum of 160 ns. The D
X
TRI-
STATE output buffer is enabled with the rising edge of FS
X
or the rising edge of BCLK
X
, whichever comes later, and the
first bit clocked out is the sign bit. The following seven
BCLK
X
rising edges clock out the remaining seven bits. The
D
X
output is disabled by the falling BCLK
X
edge following
the eighth rising edge, or by FS
X
going low, whichever
comes later. A rising edge on the receive frame sync pulse,
FS
R
, will cause the PCM data at D
R
to be latched in on the
next eight falling edges of BCLK
R
(BCLK
X
in synchronous
mode). All devices may utilize the long frame sync pulse in
synchronous or asynchronous mode.
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
seeFigure 4. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized. The op amp drives a unity-gain filter consisting of RC
active pre-filter, followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz. The output of
this filter directly drives the encoder sample-and-hold circuit.
The A/D is of companding type according to
m
-law
(TP3064) or A-law (TP3067) coding conventions. A preci-
sion voltage reference is trimmed in manufacturing to pro-
vide an input overload (t
MAX
) of nominally 2.5V peak (see
3
相關(guān)PDF資料
PDF描述
TP3067J ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO
TP3067N ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO
TP3069 “Enhanced” Serial Interface CMOS CODEC/Filter(加強(qiáng)型串行接口CMOS編解碼器/濾波器)
TP3069J ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO
TP3069N ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TP3064WM-X 功能描述:IC INTERFACE ENHANCED SER 20SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
TP3067 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:``Enhanced' Serial Interface CMOS CODEC/Filter COMBO
TP3067A 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
TP3067ADW 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TP3067AJ 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:A-Law CODEC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*