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參數(shù)資料
| 型號(hào)： | TP3064WM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| 中文描述： | MU-LAW, PCM CODEC, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, SO-20 |
| 文件頁(yè)數(shù)： | 2/18頁(yè) |
| 文件大小： | 276K |
| 代理商： | TP3064WM |
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Connection Diagrams
Dual-In-Line Package
TL/H/5070–2
Top View
Plastic Chip Carrier
TL/H/5070–6
Top View
Order Number TP3064J or TP3067J
See NS Package J20A
Order Number TP3064WM or TP3067WM
See NS Package M20B
Order Number TP3064N or TP3067N
See NS Package N20A
Order Number TP3064V or TP3067V
See NS Package V20A
Pin Description
Symbol
VPO
a
Function
The non-inverted output of the receive power
amplifier.
Analog ground. All signals are referenced to
this pin.
The inverted output of the receive power
amplifier.
Inverting input to the receive power amplifier.
Analog output of the receive filter.
Positive power supply pin. V
CC
ea
5V
g
5%.
Receive frame sync pulse which enables
BCLK
R
to shift PCM data into D
R
. FS
R
is an
8 kHz pulse train. SeeFigures 2 and3 for
timing details.
Receive data input. PCM data is shifted into
D
R
following the FS
R
leading edge.
The bit clock which shifts data into D
R
after
the FS
R
leading edge. May vary from 64 kHz
to 2.048 MHz. Alternatively, may be a logic
input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
BCLK
X
is used for both transmit and receive
directions (see Table I).
Receive master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
X
, but should be
synchronous with MCLK
X
for best
performance. When MCLK
R
is connected
continuously low, MCLK
X
is selected for all
internal timing. When MCLK
R
is connected
continuously high, the device is powered
down.
GNDA
VPO
b
VPI
VF
R
O
V
CC
FS
R
D
R
BCLK
R
/
CLKSEL
MCLK
R
/
PDN
Symbol
MCLK
X
Function
Transmit master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
R
. Best
performance is realized from synchronous
operation.
The bit clock which shifts out the PCM data
on D
X
. May vary from 64 kHz to 2.048 MHz,
but must be synchronous with MCLK
X
.
The TRI-STATE
é
PCM data output which is
enabled by FS
X
.
Transmit frame sync pulse input which
enables BCLK
X
to shift out the PCM data on
D
X
. FS
X
is an 8 kHz pulse train, seeFigures 2
and3 for timing details.
Open drain output which pulses low during
the encoder time slot.
Analog Loopback control input. Must be set
to logic ‘0’ for normal operation. When pulled
to logic ‘1’, the transmit filter input is
disconnected from the output of the transmit
preamplifier and connected to the VPO
a
output of the receive power amplifier.
Analog output of the transmit input amplifier.
Used to externally set gain.
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input
amplifier.
Negative power supply pin. V
BB
eb
5V
g
5%.
BCLK
X
D
X
FS
X
TS
X
ANLB
GS
X
VF
X
I
b
VF
X
I
a
V
BB
2
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| TP3069J | ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3064WM-X | 功能描述:IC INTERFACE ENHANCED SER 20SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| TP3067 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| TP3067A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3067ADW | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3067AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC |
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