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參數(shù)資料
| 型號： | TP3057V |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Enhanced Serial Interface CODEC/Filter COMBO Family |
| 中文描述： | A-LAW, PCM CODEC, PQCC20 |
| 封裝： | PLASTIC, CC-20 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 671K |
| 代理商： | TP3057V |
Pin Descriptions
(Continued)
Symbol
Function
MCLK
X
Transmit master clock. Must be 1.536
MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
R
. Best
performance is realized from
synchronous operation.
Transmit frame sync pulse input which
enables BCLK
X
to shift out the PCM
data on D
X
. FS
X
is an 8 kHz pulse
train, see
Figure 2
and
Figure 3
for
timing details.
The bit clock which shifts out the PCM
data on D
X
. May vary from 64 kHz to
2.048 MHz, but must be synchronous
with MCLK
X
.
The TRI-STATE
PCM data output
which is enabled by FS
X
.
Open drain output which pulses low
during the encoder time slot.
Analog output of the transmit input
amplifier. Used to externally set gain.
Inverting input of the transmit input
amplifier.
Non-inverting input of the transmit input
amplifier.
FS
X
BCLK
X
D
X
TS
X
GS
X
VF
X
I
VF
X
I
+
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initial-
izes the COMBO and places it into a power-down state. All
non-essential circuits are deactivated and the D
X
and VF
R
O
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLK
R
/PDN pin
and
FS
X
and/or FS
R
pulses must be
present. Thus, 2 power-down control modes are available.
The first is to pull the MCLK
R
/PDN pin high; the alternative is
to hold both FS
and FS
inputs continuously low—the
device will power-down approximately 1 ms after the last
FS
X
or FS
pulse. Power-up will occur on the first FS
or
FS
pulse. The TRI-STATE PCM data output, D
X
, will remain
in the high impedance state until the second FS
X
pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to MCLK
X
and the MCLK
/PDN pin can be used as a power-down
control. A low level on MCLK
/PDN powers up the device
and a high level powers down the device. In either case,
MCLK
will be selected as the master clock for both the
transmit and receive circuits.Abit clock must also be applied
to BCLK
and the BCLK
/CLKSEL can be used to select the
proper internal divider for a master clock of 1.536 MHz,
1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the
device automatically compensates for the 193rd clock pulse
each frame.
With a fixed level on the BCLK
/CLKSEL pin, BCLK
will be
selected as the bit clock for both the transmit and receive
directions.
Table 1
indicates the frequencies of operation
which can be selected, depending on the state of BCLK
R
/
CLKSEL. In this synchronous mode, the bit clock, BCLK
X
,
may be from 64 kHz to 2.048 MHz, but must be synchronous
with MCLK
X
.
Each FS
X
pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled D
X
output on the positive edge of BCLK
X
. After 8 bit
clock periods, the TRI-STATE D
X
output is returned to a high
impedance state. With an FS
R
pulse, PCM data is latched
via the D
R
input on the negative edge of BCLK
X
(or BCLK
R
if running). FS
X
and FS
R
must be synchronous with
MCLK
X/R
.
TABLE 1. Selection of Master Clock Frequencies
BCLK
R
/CLKSEL
Master Clock
Frequency Selected
TP3057
2.048 MHz
TP3054
1.536 MHz or
1.544 MHz
2.048 MHz
Clocked
0
1.536 MHz or
1.544 MHz
2.048 MHz
1
1.536 MHz or
1.544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLK
and MCLK
must be
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmis-
sion performance, however, MCLK
should be synchronous
with MCLK
, which is easily achieved by applying only static
logic levels to the MCLK
/PDN pin. This will automatically
connect MCLK
to all internal MCLK
functions (see Pin
Description). For 1.544 MHz operation, the device automati-
cally compensates for the 193rd clock pulse each frame.
FS
starts each encoding cycle and must be synchronous
with MCLK
X
and BCLK
X
. FS
R
starts each decoding cycle
and must be synchronous with BCLK
R
. BCLK
R
must be a
clock, the logic levels shown in
Table 1
are not valid in
asynchronous mode. BCLK
X
and BCLK
R
may operate from
64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
pulses, FS
and FS
, must be one bit clock period long, with
timing relationships specified in
Figure 2
. With FS
high
during a falling edge of BCLK
, the next rising edge of
BCLK
enables the D
TRI-STATE output buffer, which will
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge
disables the D
output. With FS
high during a falling edge
of BCLK
(BCLK
in synchronous mode), the next falling
edge of BCLK
latches in the sign bit. The following seven
falling edges latch in the seven remaining bits. All four de-
vices may utilize the short frame sync pulse in synchronous
or asynchronous operating mode.
T
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| TP3057V/63 | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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