參數(shù)資料
型號(hào)： TP3054WM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 編解碼器
英文描述： Enhanced Serial Interface CODEC/Filter COMBO Family
中文描述： MU-LAW, PCM CODEC, PDSO16
封裝： PLASTIC, SO-16
文件頁(yè)數(shù)： 6/16頁(yè)
文件大小： 671K
代理商： TP3054WM
Timing Specifications
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
= +5.0V
±
5%, V
= 5.0V
±
5%; T
=
40C to +85C by correlation with 100% electrical testing at T
= 25C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V
=
+5.0V, V
= –5.0V, T
= 25C. All timing parameters are assured at V
OH
= 2.0V and V
OL
= 0.7V. See Definitions and Timing
Conventions section for test methods information.
Symbol
1/t
PM
Parameter
Conditions
Min
Typ
1.536
1.544
2.048
Max
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Frequency of Master Clocks
Depends on the Device Used and the
BCLK
R
/CLKSEL Pin.
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
t
RM
t
FM
t
PB
t
RB
t
FB
t
WMH
t
WML
t
SBFM
Rise Time of Master Clock
Fall Time of Master Clock
Period of Bit Clock
Rise Time of Bit Clock
Fall Time of Bit Clock
Width of Master Clock High
Width of Master Clock Low
Set-Up Time from BCLK
X
High
to MCLK
X
Falling Edge
50
50
485
488
15725
50
50
BCLK
X
and BCLK
R
BCLK
X
and BCLK
R
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
First Bit Clock after
the Leading Edge
of FS
X
Long Frame Only
160
160
100
Short Frame
Long Frame
125
100
t
SFFM
Setup Time from FS
X
High to
MCLK
X
Falling Edge
Width of Bit Clock High
Width of Bit Clock Low
Holding Time from Bit Clock
Low to Frame Sync
Holding Time from Bit Clock
High to Frame Sync
Set-Up Time from Frame Sync
to Bit Clock Low
Delay Time from BCLK
X
High
to Data Valid
Delay Time to TS
X
Low
Delay Time from BCLK
X
Low to
Data Output Disabled
Delay Time to Valid Data from
FS
X
or BCLK
X
, Whichever
Comes Later
Set-Up Time from D
R
Valid to
BCLK
R/X
Low
Hold Time from BCLK
R/X
Low to
D
R
Invalid
Set-Up Time from FS
X/R
to
BCLK
X/R
Low
Hold Time from BCLK
X/R
Low
to FS
X/R
Low
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FS
X
or FS
R
)
Minimum Width of the Frame
Sync Pulse (Low Level)
ns
t
WBH
t
WBL
t
HBFL
V
IH
=2.2V
V
IL
=0.6V
Long Frame Only
160
160
0
ns
ns
ns
t
HBFS
Short Frame Only
0
ns
t
SFB
Long Frame Only
115
ns
t
DBD
Load=150 pF plus 2 LSTTL Loads
0
140
ns
t
DBTS
t
DZC
Load=150 pF plus 2 LSTTL Loads
C
L
=0 pF to 150 pF
140
165
ns
ns
50
t
DZF
C
L
=0 pF to 150 pF
20
165
ns
t
SDB
50
ns
t
HBD
50
ns
t
SF
Short Frame Sync Pulse (1 Bit Clock
Period Long)
Short Frame Sync Pulse (1 Bit Clock
Period Long)
Long Frame Sync Pulse (from 3 to 8 Bit
Clock Periods Long)
50
ns
t
HF
100
ns
t
HBFl
100
ns
t
WFL
64k Bit/s Operating Mode
160
ns
T
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