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參數(shù)資料
| 型號： | TP13054B |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器) |
| 中文描述： | 組合編解碼器/濾波器（單片，串行接口，組合脈沖編碼譯碼器和濾波器） |
| 文件頁數(shù)： | 5/15頁 |
| 文件大小： | 338K |
| 代理商： | TP13054B |
TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCMCODEC AND FILTER
SCTS042A – MAY 1990 – REVISED JULY 1994
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
occurs later, disables DX. A rising edge on FSR, the receive-frame sync pulse, causes the PCM data at DR to
be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync
pulse can be utilized in either the synchronous or asynchronous mode.
transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors.The low noise and wide bandwith characteristics of these devices provide gains in excess of 20 dB
across the audio passband. The operational amplifier drives a unity-gain filter consisting of an RC active prefilter
followed by an eighth-order switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. As per
μ
-law (TP3054B and TP13054B) or A-law (TP3057B
and TP13057B) coding conventions, the ADC is a companding type. A precision voltage reference provides a
nominal input overload of 2.5 V peak. The sampling of the filter output is controlled by the FSX frame-sync pulse.
Then the successive-approximation encoding cycle begins. The 8-bit code is loaded into a buffer and shifted
out through DX at the next FSX pulse. The total encoding delay is approximately 290
μ
s. Any offset voltage due
to the filters or comparator is cancelled by sign-bit integration.
receive section
The receive section consists of an expanding DAC that drives a fifth-order low-pass filter clocked at 256 kHz.
The decoder is
μ
-law (TP3054B and TP13054B) or A-law (TP3057B and TP13057B) and the fifth-order
low-pass filter corrects for the (sin x)/x attenuation caused by the 8-kHz sample/hold. The filter is followed by
a second-order RC active post-filter/power amplifier capable of driving a 600-
load to a level of 7.2 dBm. The
receive section is unity gain. At FSR, the data at DR is clocked in on the falling edge of the next eight BCLKR
(BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins and 10
μ
s later, the decoder
DAC output is updated. The decoder delay is about 10
μ
s (decoder update) plus 110
μ
s (filter delay) plus
62.5
μ
s (1/2 frame), or a total of approximately 180
μ
s.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
(see Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, V
BB
(see Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any analog input or output
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any digital input or output
. . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: TP3054B, TP3057B
TP13054B, TP13057B
Storage temperature range
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package
7 V
–7 V
V
CC
+0.3 V to V
BB
–0.3 V
V
CC
+0.3 V to ANLG GND –0.3 V
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .
0
°
C to 70
°
C
–40
°
C to 85
°
C
–65
°
C to 150
°
C
300
°
C
260
°
C
. . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
TA
≤
25
°
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
°
C
8.2 mW/
°
C
8.2 mW/
°
C
9.2 mW/
°
C
TA = 70
°
C
POWER RATING
TA = 85
°
C
POWER RATING
DW
1025 mW
656 mW
533 mW
J
1025 mW
656 mW
533 mW
N
1150 mW
736 mW
598 mW
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TP13054BDW | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054BDWR | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054BN | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13057A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP13057ADW | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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