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參數(shù)資料
| 型號： | TP13054B |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器) |
| 中文描述： | 組合編解碼器/濾波器（單片，串行接口，組合脈沖編碼譯碼器和濾波器） |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 338K |
| 代理商： | TP13054B |
TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCMCODEC AND FILTER
SCTS042A – MAY 1990 – REVISED JULY 1994
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
power up (continued)
When powering down the device, follow the steps on the previous page in reverse order. If the above procedure
cannot be followed, connect a Schottky diode between V
BB
and ground and another between V
CC
and ground.
synchronous operation
For synchronous operation, a clock is applied to MCLKX. MCLKR/PDN is used as a power-down control. A low
level on MCLKR powers up the device and a high level powers it down. In either case, MCLKX is selected as
the master clock for both receive and transmit direction. BCLKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done via BCLKR/CLKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BCLKR/CLKSEL selects BCLKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BCLKR/CLKSEL.
In the synchronous mode, BCLKX may be in the range from 64 kHz to 2.048 MHz but must be synchronous with
MCLKX.
The encoding cycle begins with each FSX pulse, and the PCM data from the previous cycle is shifted out of the
enabled DX output on the rising edge of BCLKX. After eight bit-clock periods, the 3-state DX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched via DR on the falling edge of BCLKX (or
BCLKR, if running). FSX and FSR must be synchronous with MCLKX and MCLKR.
asynchronous operation
For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must
be 2.048 MHz for the TP3057B and TP13057B, 1.536 MHz or 1.544 MHz for the TP3054B and TP13054B and
need not be synchronous. However, for best performance, MCLKR should be synchronous with MCLKX. This
is easily achieved by applying only static logic levels to MCLKR/PDN. This connects MCLKX to all internal
MCLKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame.
Each encoding cycle is started with FSX and FSX must be synchronous with MCLKX and BCLKX. Each
decoding cycle is started with FSR and FSR must be synchronous with BCLKR. The logic levels shown in
Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from 64 kHz to 2.048 MHz.
short-frame sync operation
The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically
goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing
relationships specified in Figure 1. With FSX high during a falling edge of BCLKX, the next rising edge of BCLKX
enables the 3-state output buffer, DX, which outputs the sign bits. The remaining seven bits are clocked out on
the following seven rising edges and the next falling edge disables DX. With FSR high during a falling edge of
BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following
seven falling edges latch in the seven remaining bits. The short-frame sync pulse may be utilized in either the
synchronous or asynchronous mode.
long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a short-
or long-frame sync pulse is being used. For 64-kHz operation, the frame-sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLKX, which ever occurs later, enables the DX 3-state output
buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the
remaining seven bits. The falling edge of BCLKX following the eighth rising edge or FSX going low, whichever
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP13054BDW | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054BDWR | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054BN | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13057A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP13057ADW | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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