參數(shù)資料
型號: TP11368N
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 編解碼器
英文描述: Octal Adaptive Differential PCM Processor
中文描述: A/MU-LAW, ADPCM CODEC, PDIP24
封裝: 0.600 INCH, PLASTIC, DIP-24
文件頁數(shù): 9/18頁
文件大?。?/td> 555K
代理商: TP11368N
Functional Description
(Continued)
CHANNEL NOP
Each channel can be independently disabled. When EN is at
logic low on the falling edge of CE, the ADPCM transcoder
processing for that channel is disabled. The processor re-
quires 4 CLK cycles for CE to maintain all channel variables.
The data output ports are also placed in known states. After
this the processor waits for the next interrupt. TSO outputs
the following data after a channel NOP:
TABLE 6. TSO at Channel NOP
QSEL1
0
0
1
1
The data pattern at TSO in Table 6 are shown with four
ASCK clocks within the CE high pulse for the 32- , 24-,
16-kbps modes and five ASCK clocks within the CE high
pulse for the 40 kbps mode. In the case where ASCK pulses
are more than four or five, the given pattern recirculates with
the MSB first.
In the idle state, RSO outputs the following data (bit repre-
sentation with the sign-bit on the left followed by the MSB,
the sign-bit is the first bit after the rising edge of CE):
QSEL0
0
1
0
1
Mode
32 kbps
24 kbps
16 kbps
40 kbps
TSO
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0 0
TABLE 7. RSO at Channel NOP
PCM1
0
1
Mode
8-Bit μ-Law
8-Bit A-Law
RSO
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
9
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