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參數(shù)資料
| 型號： | TP11368N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Octal Adaptive Differential PCM Processor |
| 中文描述： | A/MU-LAW, ADPCM CODEC, PDIP24 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 555K |
| 代理商： | TP11368N |
Functional Description
(Continued)
the falling edge of CE are latched in. In Table 3 the last input
bit prior to to the CE falling edge is the LSB of the ADPCM
data word.
Note that the serial input data is referenced to the falling
edge of CE while the serial output data is referenced to the
rising edge of CE.
Table 4 shows the transfer order of the ADPCM output data.
In the case where there are more ASCK clocks than the AD-
PCM data, the ADPCM output will recirculate.
For example, if the 32 kbps mode is selected, and eight low
pulses of ASCK exist within the CE high pulse, the following
ADPCM encoded data D3-D2-D1-D0-D3-D2-D1-D0 will ap-
pear at the TSO output (Table 5).
TABLE 3. Transfer Order of ADPCM Input Data (RSI). The Last Bit Prior[to] the Falling Edge of CE is the LSB of the
ADPCM Data
QSEL1
0
0
1
1
QSEL0
0
1
0
1
Mode
32 kbps
24 kbps
16 kbps
40 kbps
Bit 5
x
x
x
D4
(MSB)
Bit 4
D3
D2
D1
D3
Bit 3
D2
D1
D0
D2
Bit 2
D1
D0
x
D1
Bit 1
D0
x
x
D0
(LSB)
Note 1:
x = Don’t Care state
TABLE 4. Transfer Order of ADPCM Output Data (TSO) with 4 ASCK Rising Edgesile CE is High (the First Bit is the
MSB Data Bit following the Rising Edge of CE)
QSEL1
0
0
1
1
QSEL0
0
1
0
1
Mode
32 kbps
24 kbps
16 kbps
40 kbps
Bit 5
D3
D2
D1
D4
(MSB)
Bit 4
D2
D1
D0
D3
Bit 3
D1
D0
x
D2
Bit 2
D0
x
x
D1
Bit 1
D3
D2
D1
D0
(LSB)
Note 2:
x = unknown (but defined) state
TABLE 5. Transfer Order of ADPCM Output Data (TSO)th 7 Rising Edges (7 Low Pulses) while CE is High
QSEL1
0
0
1
1
QSEL0
0
1
0
1
Mode
32 kbps
24 kbps
16 kbps
40 kbps
Bit 8
D3
D2
D1
D4
Bit 7
D2
D1
D0
D3
Bit 6
D1
D0
x
D2
Bit 5
D0
x
x
D1
Bit 4
D3
D2
D1
D0
Bit 3
D2
D1
D0
D4
Bit 2
D1
D0
x
D3
Bit 1
D0
x
x
D2
Note 3:
x = unknown (but defined) state
SINGLE-CHANNEL INITIALIZATION AND
ALL-CHANNEL RESET
The TP11368 ADPCM processor can be initialized on a
per-channel basis via the use of INIT or on an all-channel ba-
sis via the use of RSTB. In both cases, the internal ADPCM
variables are initialized to the default values as suggested by
the ITU G.726 recommendation.
An individual channel can be initialized to the desired con-
figuration by setting the corresponding data variables PCM1,
EN, QSEL(0,1) and by asserting the INIT pin high. The con-
figuration data and INIT signal are strobed at the falling edge
of CE. For an initialization cycle, the period of CE must be 45
master clock (CLK) cycles. The transcoder is then ready to
process the next channel.
The active low RSTB signal is used for a “warm” reset as
well as for facilitating device testing. The initialization of the
internal memory takes 726 CLK cycles after the RSTB goes
inactive (logic “1”). The first transition of CE is allowed six
CLK cycles after RSTB goes inactive. It is recommended
that CE be kept low during the initialization phase.The rec-
ommended values for ASCK and PSCK during initialization
are logic “1”, and that for TSI and RSI logic “0”.Any data (TSI
and RSI) applied during the initialization phase will be lost,
however, they won’t affect the proper initialization process.
The minimum low time of RSTB is 2 CLK cycles.
The chip resumes operation on the first negative edge of CE
after the completion of the initialization.
POWER-ON-RESET
The on-chip Power-On-Reset macro is activated when exter-
nal power is first applied to the device. It has the same func-
tion as the external RSTB pin which initializes all channels to
the default values defined in the ITU Recommendation
G.726. At power up, the outputs TSO and RSO are in
TRI-STATE mode. This “cold” reset process is asynchronous
and takes approximately 2000 CLK cycles for the initializa-
tion.
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| TP11368V | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| TP11368V/NOPB | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| TP11368VNOPB | 制造商:National Semiconductor 功能描述:Octal Adaptive Differential PCM Processor 28-Pin PLCC Tube |
| TP1138JB/TR | 制造商:Alpha 3 Manufacturing 功能描述: |
| TP1143 | 制造商:2B 功能描述: |
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