參數(shù)資料
型號： TNT4882-BQ
英文描述： Peripheral Miscellaneous
中文描述： 周邊雜項
文件頁數(shù)： 3/16頁
文件大?。?/td> 165K
代理商： TNT4882-BQ
TNT4882
Single-Chip IEEE 488.2 Talker/Listener ASIC
National Instruments
Phone: (512) 794-0100 Fax: (512) 683-9300 info@natinst.com www.natinst.com
3
D
G
L
D
G
I
D
S
G
D
A
R
G
R
80 79 78 77 76 75 74 73 72
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
71 70 69 68 67 66 65 64
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
G
DATA5
DATA4
GND
DATA3
DATA2
DATA1
GND
VDD
GND
VDD
GND
INTR
DACKN
DRQ
BURST_RDN
DATA0
RDY1
DAVN
EOIN
GND
VDD
DIO4N
GND
DIO2N
DIO1N
GND
DIO3N
VDD
XTAL0
XTAL1
GND
KEYCLKN
KEYDQ
KEYRSTN
W
G
V
T
C
T
A
A
A
A
A
A
A
P
G
R
S
F
TNT4882
Generic Pin Configuration
V
18 19 20 21 22 23 24 25 26 27 28 29 30
D
G
D
D
D
G
D
D
B
D
D
V
G
48
GND
49
DATA6
50
DATA7
63
R
62
B
61
G
60
V
59
G
58
V
57
G
56
G
55
C
54
G
53
M
52
N
51
D
83
GND
82
NRFDN
81
NDACN
Generic Pin Configuration
Figure 3. TNT4882 Generic Pin Configuration
Table continued on page 4
Pin No.(s)
1
2,3,5,6,7,9,10,11
Name(s)
BBUS_OEN
DATA15-8
Type
O
I/O
Description
Asserts when DATA7-0 (B bus) is enabled for output
Upper 8 bits of bidirectional three-state data bus for transfer of commands, data, and status
between TNT4882 and CPU – also known as the A bus
Enables register accesses through the A bus (DATA15-8) – DATA15 is the most significant bit
Determines which register to access during a read or write operation
Asserts when DATA15-8 (A bus) is enabled for output
Asserts when the TNT4882 is an active or addressed IEEE 488 Talker (TADS, TACS, or SPAS)
Asserts in two-chip mode during a NAT4882 register I/O access
Asserts when in DTAS or when the auxiliary trigger software command is issued
Asserting this pin pages in the page-in registers in the 7210 mode
Asserts when the TNT4882 is in a remote state (REMS or RWLS)
Rearranges the order of the registers when asserted and in 9914 mode
Asserts when the FIFO is ready for burst access
When asserted, places the TNT4882 in a burst read mode, in which the first word in the
FIFO is always driven on the TNT4882 data bus – words are removed from the FIFOs at
each rising edge of RDN – see reference manual for details
Asserts to request a DMA transfer cycle
Enables FIFO accesses during a DMA transfer cycle
Asserts when one or more of the unmasked interrupt conditions becomes true
Asserts during an I/O access to indicate that the read data is available or that the write
data has been latched – asserts immediately on an access to Turbo488 registers or in
one-chip mode
Lower eight bits of bidirectional three-state data bus for transfer of commands, data, and
status between TNT4882 and CPU – also known as the B bus – DATA7 is the most significant bit
14
19-15
20
21
22
23
26
28
29
30
31
ABUSN
ADDR4-0
ABUS_OEN
TADCS
CPUACC
TRIG
PAGED
REM
SWAPN
FIFO_RDY
BURST_RDN
I
I
O
O
O
O
I
O
I
O
I
32
33
34
38
DRQ
DACKN
INTR
RDY1
O
I
O
O
50,49,4746,
44,43,42,39
DATA7-0
I/O
Generic Pin Description
All pins with names that end in ‘N’ are active low; all others are active high. All input (I) and bidirectional (I/O) pins have an internal pull-up
resistor between 50 k
and 150 k
.
Note: You can also see the “Hardware Considerations” chapter of the “TNT Programmer Reference Manual” (P/N 320724-01) for more
information.
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