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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
8.7.3.9
PLLDIV Ratio Change Status Register
Whenever a different ratio is written to the PLLDIV
n
registers, the PLLCTRL flags the change in the
PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will only
change the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be
automatically aligned to other clocks. The PLLDIV divider ratio change status register is shown in
Figure 8-19
and described in
Table 8-27
.
31
16
Reserved
R-0
15
5
4
3
2
0
Reserved
SYS5
SYS4
Reserved
R-0
R-0
R-0
R-0
LEGEND:
R/W = Read/Write; R = Read only; -
n
= value after reset
Figure 8-19. PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029A 0144]
Table 8-27. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31:5
4
Field
Reserved
SYS5
Value
0
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Identifies when the SYSCLK5 divide ratio has been modified.
SYSCLK5 ratio has not been modified. When GOSET is set, SYSCLK5 will not be affected.
SYSCLK5 ratio has been modified. When GOSET is set, SYSCLK5 will change to the new ratio.
Identifies when the SYSCLK4 divide ratio has been modified.
SYSCLK4 ratio has not been modified. When GOSET is set, SYSCLK4 will not be affected.
SYSCLK4 ratio has been modified. When GOSET is set, SYSCLK4 will change to the new ratio.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0
1
3
SYS4
0
1
0
2:0
Reserved
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C64x+ Peripheral Information and Electrical Specifications
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