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參數(shù)資料
| 型號(hào)： | TMX320TCI6482 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Communications Infrastructure Digital Signal Processor |
| 中文描述： | 通信基礎(chǔ)設(shè)施的數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 3/255頁(yè) |
| 文件大?。?/td> | 1893K |
| 代理商： | TMX320TCI6482 |
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www.ti.com
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
The TCI6482 DSP integrates a large amount of on-chip memory organized as a two-level memory system.
The level-1 (L1) program and data memories on the TCI6482 device are 32KB each. This memory can be
configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1
program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The
level 2 (L2) memory is shared between program and data space and is 2096KB in size. L2 memory can
also be configured as mapped RAM, cache, or some combination of the two. The C64x+ Megamodule
also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system
component with reset/boot control, interrupt/exception control, a power-down control, and a free-running
32-bit timer for time stamp.
The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial
ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode
(ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit
timers); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component
interconnect (PCI); a 16-pin general-purpose input/output port (GPIO) with programmable interrupt/event
generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which provides an efficient
interface between the TCI6482 DSP core processor and the network; a management data input/output
(MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system; a 4-bit transmit, 4-bit receive VLYNQ interface; a glueless
external memory interface (64-bit EMIFA), which is capable of interfacing to synchronous and
asynchronous peripherals; and a 32-bit DDR2 SDRAM interface.
The I2C ports on the TCI6482 allows the DSP to easily control peripheral devices and communicate with a
host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to
communicate with serial peripheral interface (SPI) mode peripheral devices.
The VLYNQ interface provides a standard high-speed serial interface to a variety of TI devices that can
supplement the processing power or external connectivity of the TCI6482 device. This supports
host-to-peripheral or peer-to-peer communication modes.
The TCI6482 device has two high-performance embedded coprocessors [enhanced Viterbi Decoder
Coprocessor (VCP2) and enhanced Turbo Decoder Coprocessor (TCP2)] that significantly speed up
channel-decoding operations on-chip. The VCP2 operating at CPU clock divided-by-3 can decode over
694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint
lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5 and flexible polynomials, while
generating hard decisions or soft decisions. The TCP2 operating at CPU clock divided-by-3 can decode
up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2
implements the max*log-map algorithm and is designed to support all polynomials and rates required by
Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and
turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also
programmable. Communications between the VCP2/TCP2 and the CPU are carried out through the
EDMA3 controller.
The TCI6482 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into
source code execution.
The C64x+ CPU has two tightly coupled Rake/Search Accelerators (RSAs) for Code Division Multiple
Access (CDMA) to assist with chip rate processing in Base Transceiver Systems (BTS).
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