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參數(shù)資料
| 型號： | TMX320TCI6482 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Communications Infrastructure Digital Signal Processor |
| 中文描述： | 通信基礎(chǔ)設(shè)施的數(shù)字信號處理器 |
| 文件頁數(shù)： | 125/255頁 |
| 文件大?。?/td> | 1893K |
| 代理商： | TMX320TCI6482 |
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www.ti.com
8.6 Reset Controller
8.6.1
Power-on Reset (POR Pin)
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
The reset controller detects the different type of resets supported on the TCI6482 device and manages the
distribution of those resets throughout the device.
The TCI6482 device has several types of resets: power-on reset, warm reset, max reset, system reset,
and CPU reset.
Table 8-12
explains further the types of reset, the reset initiator, and the effects of each
reset on the chip. For more information on the effects of each reset on the PLL controllers and their
clocks, see
Section 8.6.8
,
Reset Electrical Data/Timing
.
Table 8-12. Reset Types
TYPE
INITIATOR
EFFECT(s)
Power-on Reset
POR pin
Resets the entire chip including the test and emulation logic.
Resets everything except for the test and emulation logic and PLL2.
Emulator stays alive during Warm Reset.
Same as Warm Reset.
A system reset maintains memory contents and does not reset the
test and emulation circuitry. The device configuration pins are also
not re-latched and the state of the peripherals is also not affected.
(2)
CPU local reset.
Warm Reset
RESET pin
Max Reset
RapidIO [through INTDST5
(1)
]
System Reset
Emulator
CPU Local Reset
HPI/PCI
(1)
INTDST5 is used generate a MAX reset only. It is not connected to the device interrupt controller. For more detailed information on the
INTDST5, see the
TMS320TCI648x DSP Serial Rapid I/O User's Guide
(literature number
SPRUE13
).
On the TCI6482 device, peripherals can be in one of several states. These states are listed in
Table 3-4
.
(2)
Power-on Reset is initiated by the POR pin and is used to reset the entire chip, including the test and
emulation logic. Power-on Reset is also referred to as a cold reset since the device usually goes through a
power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power supplies
have reached their normal operating conditions. Note that a device power-up cycle is not required to
initiate a Power-on Reset.
The following sequence must be followed during a Power-on Reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted
(driven low).
While POR is asserted, all pins will be set to high-impedance. After the POR pin is deasserted (driven
high), all Z group pins, low group pins, and high group pins are set to their reset state and will remain
at their reset state until the otherwise configured by their respective peripheral. All peripherals, except
those selected for boot purposes, are disabled after a Power-on Reset and must be enabled through
the Device State Control registers; for more details, see
Section 3.3
,
Peripheral Selection After Device
Reset
.
2. Once all the power supplies are within valid operating conditions, the POR pin must remain asserted
(low) for a minimum of 256 CLKIN2 cycles. The PLL1 controller input clock, CLKIN1, and the PCI input
clock, PCLK, must also be valid during this time. PCLK is only needed if the PCI module is being used.
If the DDR2 memory controller and the EMAC peripheral are not needed, CLKIN2 can be tied low and,
in this case, the POR pin must remain asserted (low) for a minimum of 256 CLKIN1 cycles after all
power supplies have reached valid operating conditions.
Within the low period of the POR pin, the following happens:
–
The reset signals flow to the entire chip (including the test and emulation logic), resetting modules
that use reset asynchronously.
–
The PLL1 controller clocks are started at the frequency of the system reference clock. The clocks
are propagated throughout the chip to reset modules that use reset synchronously. By default,
PLL1 is in reset and unlocked.
–
The PLL2 controller clocks are started at the frequency of the system reference clock. PLL2 is held
in reset. Since the PLL2 controller always operates in PLL mode, the system reference clock and
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C64x+ Peripheral Information and Electrical Specifications
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