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TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
List of Tables
2-1
Hardware Features
 ...............................................................................................................
 11
Signal Descriptions
 ...............................................................................................................
 14
Addresses of Flash Sectors
 .....................................................................................................
 22
Wait-states
.........................................................................................................................
 23
Boot Mode Selection
..............................................................................................................
 25
Peripheral Frame 0 Registers
...................................................................................................
 29
Peripheral Frame 1 Registers
...................................................................................................
 30
Peripheral Frame 2 Registers
...................................................................................................
 30
Device Emulation Registers
 .....................................................................................................
 30
PIE Peripheral Interrupts
.........................................................................................................
 32
PIE Configuration and Control Registers
 ......................................................................................
 33
External Interrupt Registers
......................................................................................................
 33
PLL, Clocking, Watchdog, and Low-Power Mode Registers
................................................................
 35
PLLCR Register Bit Definitions
..................................................................................................
 37
Possible PLL Configuration Modes
.............................................................................................
 38
Low-Power Modes
................................................................................................................
 40
CPU-Timers 0, 1, 2 Configuration and Control Registers
 ...................................................................
 42
ePWM1-4 Control and Status Registers
.......................................................................................
 44
ePWM5-8 Control and Status Registers
.......................................................................................
 45
ePWM9-12 Control and Status Registers
......................................................................................
 46
ePWM13-16 Control and Status Registers
....................................................................................
 47
ADC Registers
.....................................................................................................................
 53
SCI-A Registers
...................................................................................................................
 55
SPI-A Registers
 ...................................................................................................................
 58
I
2
C-A Registers
....................................................................................................................
 61
GPIO Registers
 ...................................................................................................................
 63
F28044 GPIO MUX Table
........................................................................................................
 64
TMS320F28044 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
 .............................
 73
Typical Current Consumption by Various Peripherals (at 100 MHz)
.......................................................
 74
TMS320x280x Clock Table and Nomenclature
...............................................................................
 77
Input Clock Frequency
 ...........................................................................................................
 78
XCLKIN Timing Requirements - PLL Enabled
 ................................................................................
 78
XCLKIN Timing Requirements - PLL Disabled
................................................................................
 78
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
.........................................................
 78
Power Management and Supervisory Circuit Solutions
......................................................................
 79
Reset (XRS) Timing Requirements
 ............................................................................................
 81
General-Purpose Output Switching Characteristics
..........................................................................
 82
General-Purpose Input Timing Requirements
.................................................................................
 83
IDLE Mode Timing Requirements
...............................................................................................
 85
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
List of Tables
6
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