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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 3-56. EMIFA/VPSS Sub-Block 0 Pin-By-Pin Mux Control
MULTIPLEXED FUNCTIONS
EMIFA ADDR/CTRL
(AEM[2:0] = 1, 3)
EMIFA DATA
(AEM[2:0] = 3, 4)
SIGNAL NAME
VPFE
PCI
GPIO
FUNCTION
SELECT
FUNCTION
SELECT
FUNCTION
SELECT
FUNCTION
SELECT
FUNCTION
SELECT
PCLK/GP[54]
PCLK
CCDCSEL = 1
–
–
–
–
–
–
GP[54]
CCDCSEL = 0
YI7(CCD7)/GP[43]
YI7(CCD7)
–
–
–
–
–
–
GP[43]
YI6(CCD6)/GP[42]
YI6(CCD6)
–
–
–
–
–
–
GP[42]
YI5(CCD5)/GP[41]
YI5(CCD5)
–
–
–
–
–
–
GP[41]
YI4(CCD4)/GP[40]
YI4(CCD4)
–
–
–
–
–
–
GP[40]
YI3(CCD3)/GP[39]
YI3(CCD3)
–
–
–
–
–
–
GP[39]
YI2(CCD2)/GP[38]
YI2(CCD2)
–
–
–
–
–
–
GP[38]
YI1(CCD1)/GP[37]
YI1(CCD1)
–
–
–
–
–
–
GP[37]
YI0(CCD0)/GP[36]
YI0(CCD0)
–
–
–
–
–
–
GP[36]
VD/GP[53]
VD
HVDSEL = 1
–
–
–
–
–
–
GP[53]
HVDSEL = 0
HD/GP[52]
HD
–
–
–
–
–
–
GP[52]
CI7(CCD15)/EM_A[13]/
AD25/EM_D[0]/GP[51]
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0,
CI76SEL = 1
PCIEN = 0,
AEM = 1,
AEAW = 1/2/3/4,
CI76SEL = 0
PCIEN = 0,
AEM = 3/4,
AEAW = 0,
CI76SEL = 0
PCIEN = 1,
AEM = 0/5,
AEAW = 0,
CI76SEL = 0
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0,
CI76SEL = 0
CI7(CCD15)
EM_A[13]
EM_D[0]
AD25
GP[51]
CI6(CCD14)/EM_A[14]/
AD27/EM_D[1]/GP[50]
CI6(CCD14)
EM_A[14]
EM_D[1]
AD27
GP[50]
CI5(CCD13)/EM_A[15]/
AD29/EM_D[2]/GP[49]
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1
(1)
,
CI54SEL = 1
PCIEN = 0,
AEM = 1,
AEAW = 2/3/4,
CI54SEL = 0
PCIEN = 0,
AEM = 3/4,
AEAW = 0,
CI54SEL = 0
PCIEN = 1,
AEM = 0/5,
AEAW = 0,
CI54SEL = 0
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1 ,
CI54SEL = 0
CI5(CCD13)
EM_A[15]
EM_D[2]
AD29
GP[49]
CI4(CCD12)/EM_A[16]/
PGNT/EM_D[3]/GP[48]
CI4(CCD12)
EM_A[16]
EM_D[3]
PGNT
GP[48]
CI3(CCD11)/EM_A[17]/
AD31/EM_D[4]/GP[47]
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1/2
(1)
,
CI32SEL = 1
PCIEN = 0,
AEM = 1,
AEAW = 3/4,
CI32SEL = 0
PCIEN = 0,
AEM = 3/4,
AEAW = 0,
CI32SEL = 0
PCIEN = 1,
AEM = 0/5,
AEAW = 0,
CI32SEL = 0
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1/2 ,
CI32SEL = 0
CI3(CCD11)
EM_A[17]
EM_D[4]
AD31
GP[47]
CI2(CCD10)/EM_A[18]/
PRST/EM_D[5]/GP[46]
CI2(CCD10)
EM_A[18]
EM_D[5]
PRST
GP[46]
CI1(CCD9)/EM_A[19]/
PREQ/EM_D[6]/GP[45]
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1/2/3
(1)
,
CI10SEL = 1
PCIEN = 0,
AEM = 1,
AEAW = 4,
CI10SEL = 0
PCIEN = 0,
AEM = 3/4,
AEAW = 0,
CI10SEL = 0
PCIEN = 1,
AEM = 0/5,
AEAW = 0,
CI10SEL = 0
PCIEN = 0,
AEM = 0/1/5,
AEAW = 0/1/2/3 ,
CI10SEL = 0
CI1(CCD9)
EM_A[19]
EM_D[6]
PREQ
GP[45]
CI0(CCD8)/EM_A[20]/
PINTA/EM_D[7]/GP[44]
CI0(CCD8)
EM_A[20]
EM_D[7]
PINTA
GP[44]
C_WE/EM_R/W/GP[35]
CWENSEL = 1,
AEM = 0/4/5
CWENSEL = 0,
AEM = 1/3
–
–
CWENSEL = 0,
AEM = 0/4/5
C_WE
EM_R/W
–
–
GP[35]
C_FIELD/EM_A[21]/GP[34]
CFLDSEL = 1,
AEM = 0/1/3/4/5
CFLDSEL = 0,
AEM = 1
–
–
CFLDSEL = 0,
AEM = 0/3/4/5
C_FIELD
EM_A[21]
–
–
GP[34]
(1)
AEAW = 1/2/3/4 is only valid if AEM[2:0] = 1.
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