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P
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A–APRIL 2006–REVISED DECEMBER 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE
(1)
IPD/IPU
(2)
DESCRIPTION
NO.
Nonmaskable interrupt, edge-driven (rising edge)
Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin
is not used, it is recommended that the NMI pin be grounded versus relying on
the IPD.
Reset Status pin. The RESETSTAT pin indicates when the device is in reset
Power on reset.
NMI
AH4
I
IPD
RESETSTAT
POR
GP[7]
GP[6]
GP[5]
GP[4]
PREQ/GP[15]
PINTA
(5)
/GP[14]
PRST/GP[13]
PGNT/GP[12]
FSX1/GP[11]
FSR1/GP[10]
DX1/GP[9]
DR1/GP[8]
CLKX1/GP[3]
PCBE0/GP[2]
SYSCLK4/GP[1]
(3)
CLKR1/GP[0]
AE14
AF14
AG2
AG3
AJ2
AH2
P2
P3
R5
R4
AG4
AE5
AG5
AH5
AF5
P1
AJ13
AF4
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI)
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and
GP[15:8], or PCI peripherals. This pin works in conjunction with the
Y29
I
IPD
MCBSP
1
_EN (AEA5 pin) to enable/disable other peripherals (for more details,
see
Section 3
,
Device Configuration
).
U3
I/O/Z
Host interrupt from DSP to host (
O/Z
) or PCI frame (
I/O/Z
)
Host control - selects between control, address, or data registers (
I
) [default] or
U4
I/O/Z
PCI device select (
I/O/Z
)
Host control - selects between control, address, or data registers (
I
) [default] or
U5
I/O/Z
PCI stop (
I/O/Z
)
Host half-word select - first or second half-word (not necessarily high or low
V3
I/O/Z
order)
[For HPI16 bus width selection only] (
I
) [default] or PCI clock (
I
)
T5
I/O/Z
Host read or write select (
I
) [default] or PCI command/byte enable 2 (
I/O/Z
)
T3
I/O/Z
Host address strobe (
I
) [default] or PCI parity (
I/O/Z
)
U6
I/O/Z
Host chip select (
I
) [default] or PCI parity error (
I/O/Z
)
U2
I/O/Z
Host data strobe 1 (
I
) [default] or PCI system error (
I/O/Z
)
U1
I/O/Z
Host data strobe 2 (
I
) [default] or PCI command/byte enable 1 (
I/O/Z
)
T4
I/O/Z
Host ready from DSP to host (
O/Z
) [default] or PCI initiator ready (
)
P2
I/O/Z
PCI bus request (
O/Z
) or GP[15] (
I/O/Z
) [default]
P3
I/O/Z
PCI interrupt A (
O/Z
) or GP[14] (
I/O/Z
) default]
R5
I/O/Z
PCI reset (
I
) or GP[13] (
I/O/Z
) [default]
R4
I/O/Z
PCI bus grant (
I
) or GP[12] (
I/O/Z
)[default]
P1
I/O/Z
PCI command/byte enable 0 (
I/O/Z
) or GP[2] (
I/O/Z
)[default]
P5
I/O/Z
PCI command/byte enable 3 (
I/O/Z
). By default, this pin has no function.
R3
I
PCI initialization device select (
I
). By default, this pin has no function.
O
I
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
O/Z
I/O/Z
IPD
IPD
IPD
IPD
General-purpose input/output (GPIO) pins (
I/O/Z
).
PCI peripheral pins or general-purpose input/output (GPIO) [15:12, 2] pins
(
I/O/Z
) [default]
PCI bus request (
O/Z
) or GP[15] (
I/O/Z
) [default]
PCI interrupt A (
O/Z
) or GP[14] (
I/O/Z
) [default]
PCI reset (
I
) or GP[13] (
I/O/Z
) [default]
PCI bus grant (
I
) or GP[12] (
I/O/Z
) [default]
PCI command/byte enable 0 (
I/O/Z
) or GP[2] (
I/O/Z
) [default]
IPD
IPD
IPD
IPD
IPD
McBSP1 transmit clock (
I/O/Z
) or GP[3] (
I/O/Z
) [default]
McBSP1 receive clock (
I/O/Z
) or GP[0] (
I/O/Z
) [default]
GP[1] pin (
I/O/Z
). SYSCLK4 is the clock output at 1/8 of the device speed (
O/Z
)
or this pin can be programmed as a GP[1] pin (
I/O/Z
) [default].
IPD
IPD
PCI_EN
HINT/PFRAME
HCNTL1/PDEVSEL
HCNTL0/PSTOP
HHWIL/PCLK
HR/W/PCBE2
HAS/PPAR
HCS/PPERR
HDS1/PSERR
(5)
HDS2/PCBE1
HRDY/PIRDY
PREQ/GP[15]
PINTA
(5)
/GP[14]
PRST/GP[13]
PGNT/GP[12]
PCBE0/GP[2]
PCBE3
PIDSEL
(5)
These pins function as open-drain outputs when configured as PCI pins.
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