參數(shù)資料
型號: TMX320C6413ZTSA500
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 46/140頁
文件大?。?/td> 1958K
代理商: TMX320C6413ZTSA500
Device Configurations
46
April 2004
Revised May 2005
SPRS247E
3.3
Peripheral Selection After Device Reset
HPI, McBSP1, McBSP0, McASP1, McASP0, I2C1, and I2C0
The C6413/C6410 device has designated registers for peripheral configuration (PERCFG), device status
(DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration module
and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these registers via the
CFGBUS.
The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the
McASP1, McASP0, I2C1, and I2C0 peripherals. For more detailed information on the PERCFG register
control bits, see Figure 3
1 and Table 3
3.
31
28
27
24
Reserved
Reserved
R-0
R-0
23
16
Reserved
R-0
15
11
10
9
8
Reserved
AFCMUX[1:0]
MCASP1EN
R-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
I2C1EN
Reserved
Reserved
Reserved
I2C0EN
MCBSP1EN
MCBSP0EN
MCASP0EN
R/W-0
R-0
R-0
R-0
R/W-0
R-1
R-1
R/W-0
Legend:
R = Read only; R/W = Read/Write; -n = value after reset
For proper device operation, all reserved bits have to be written with “0”.
Figure 3
1. Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000]
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