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型號(hào)：	TMS664814DGE-8A
英文描述：	SDRAM\|4X2MX8\|CMOS\|TSOP\|54PIN\|PLASTIC
中文描述：	內(nèi)存\| 4X2MX8 \|的CMOS \|的TSOP \| 54PIN \|塑料
文件頁(yè)數(shù)：	24/56頁(yè)
文件大小：	958K
代理商：	TMS664814DGE-8A

TMS664414, TMS664814, TMS664164

4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES

SMOS695A – APRIL 1998 – REVISED JULY 1998

POST OFFICE BOX 1443

HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

general information for ac timing measurements

The ac timing measurements are based on signal rise and fall times equal to 1 ns (t

= 1 ns) and a midpoint

reference level of 1.5 V (INPUT = 2.8 V, 0 V) for LVTTL. For signal rise and fall times greater than 1 ns, the

reference level should be changed to V

MIN and V

MAX instead of the midpoint level. All specifications

referring to READ commands are valid for READ-P commands unless otherwise noted. All specifications

referring to WRT commands are also valid for WRT-P commands unless otherwise noted. All specifications

referring to consecutive commands are specified as consecutive commands for the same bank unless

otherwise noted.

Output

Under

Test

CL = 50 pF

Z = 50

Figure 9. ac Load Circuit

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