參數(shù)資料
型號(hào)： TMS6644148A
廠商： Texas Instruments, Inc.
英文描述： 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
中文描述： 4 194 304 4位/ 2 097 152 8位/ 1 048 576由16位4，銀行同步動(dòng)態(tài)隨機(jī)存取記憶體
文件頁(yè)數(shù)： 13/56頁(yè)
文件大?。?/td> 958K
代理商： TMS6644148A
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
setting the mode register
The ’664xx4 contains a mode register that must be user-programmed with the CAS latency, the burst type, and
the burst length. This is accomplished by executing an MRS command with the information entered on address
lines A0–A9. A logic 0 must be entered on A7 and A8, but A10–A13 are “don’t care” entries for the ’664xx4.
When A9 = 1, the write burst length is always 1. When A9 = 0, the write burst length is defined by A2–A0.
Figure 2 shows the valid combinations for a successful MRS command. Only valid addresses allow the mode
register to be changed. If the addresses are not valid, the previous contents of the mode register remain
unaffected. The MRS command is executed by holding RAS, CAS, and W low and the input-mode word valid
on A0–A9 on the rising edge of CLK (see Table 1). The MRS command can be executed only when all banks
are deactivated and may not be executed while a burst is active. See Figure 24 and Figure 35 for examples.
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Reserved
0 = Serial
1 = Interleave
(burst type)
0
0
A13
A12
REGISTER
BIT A9
WRITE
BURST
LENGTH
REGISTER
BITS
CAS
REGISTER
BITS
BURST LENGTH
A6
A5
A4
LATENCY§
A2
A1
A0
0
1
A2–A0
1
0
0
1
1
0
1
2
3
0
0
0
0
0
0
1
1
0
1
0
1
1
2
4
8
All other combinations are reserved.
Refer to timing requirements for minimum valid read latencies based on maximum frequency rating.
§Once the mode register has been set, subsequent changes to the CAS latency is prohibited.
Figure 2. Mode-Register Programming
refresh
The ’664xx4 must be refreshed at intervals not exceeding t
REF
(see timing requirements) or data cannot be
retained. Refresh is accomplished by performing one of the following:
An ACTV command (RAS-only refresh) to every row in all banks
4096 auto-refresh (REFR) commands
Putting the device in self-refresh mode
Regardless of the method used, refresh must be accomplished before t
REF
has expired. See Figure 34 for an
example.
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TMS664414DGE-8 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SDRAM|4X4MX4|CMOS|TSOP|54PIN|PLASTIC
TMS664414DGE-8A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SDRAM|4X4MX4|CMOS|TSOP|54PIN|PLASTIC
TMS664814 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
TMS66481410 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
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